Using sdram_control_4Port module in VHDL

All,

I am new to VHDL. I am trying to use the sdram_control_4Port form the terasic to read and write to SDRAM. The end goal is to use the TRDB_D5M camera to capture and image then modify the data in the SDRAM and display the image on the screen.

The hardware platform is DE2-70 board

Bellow is my code. Any help is appreciated.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY final_project IS

PORT (

--////////////////// Clock Input ////////////////////

iCLK_28 : IN STD_LOGIC; -- 28.63636 MHz

iCLK_50 : IN STD_LOGIC; -- 50 MHz

iCLK_50_2 : IN STD_LOGIC; -- 50 MHz

iCLK_50_3 : IN STD_LOGIC; -- 50 MHz

iCLK_50_4 : IN STD_LOGIC; -- 50 MHz

iEXT_CLOCK : IN STD_LOGIC; -- External Clock

--////////////////// Push Button ////////////////////

iKEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Pushbutton[3:0]

--////////////////// DPDT Switch ////////////////////

iSW : IN STD_LOGIC_VECTOR(17 DOWNTO 0); -- Toggle Switch[17:0]

--///////////////////// SDRAM Interface ////////////////

DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- SDRAM Data bus 32 Bits

oDRAM0_A : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); -- SDRAM0 Address bus 13 Bits

oDRAM1_A : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); -- SDRAM1 Address bus 13 Bits

oDRAM0_LDQM0: OUT STD_LOGIC; -- SDRAM0 Low-byte Data Mask

oDRAM1_LDQM0: OUT STD_LOGIC; -- SDRAM1 Low-byte Data Mask

oDRAM0_UDQM1: OUT STD_LOGIC; -- SDRAM0 High-byte Data Mask

oDRAM1_UDQM1: OUT STD_LOGIC; -- SDRAM1 High-byte Data Mask

oDRAM0_WE_N : OUT STD_LOGIC; -- SDRAM0 Write Enable

oDRAM1_WE_N : OUT STD_LOGIC; -- SDRAM1 Write Enable

oDRAM0_CAS_N: OUT STD_LOGIC; -- SDRAM0 Column Address Strobe

oDRAM1_CAS_N: OUT STD_LOGIC; -- SDRAM1 Column Address Strobe

oDRAM0_RAS_N: OUT STD_LOGIC; -- SDRAM0 Row Address Strobe

oDRAM1_RAS_N: OUT STD_LOGIC; -- SDRAM1 Row Address Strobe

oDRAM0_CS_N : OUT STD_LOGIC; -- SDRAM0 Chip Select

oDRAM1_CS_N : OUT STD_LOGIC; -- SDRAM1 Chip Select

oDRAM0_BA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); -- SDRAM0 Bank Address

oDRAM1_BA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); -- SDRAM1 Bank Address

oDRAM0_CLK : OUT STD_LOGIC; -- SDRAM0 Clock

oDRAM1_CLK : OUT STD_LOGIC; -- SDRAM1 Clock

oDRAM0_CKE : OUT STD_LOGIC; -- SDRAM0 Clock Enable

oDRAM1_CKE : OUT STD_LOGIC; -- SDRAM1 Clock Enable

--/////////////////////// LED ////////////////////////

oLEDG : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); -- LED Green[8:0]

oLEDR : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) -- LED Red[15:0]

);

END final_project;

ARCHITECTURE circuit OF final_project IS

SIGNAL sdram_ctrl_clk: STD_LOGIC ;

SIGNAL WR1_FULL,WR2_FULL,RD1_EMPTY,RD2_EMPTY: STD_LOGIC ;

SIGNAL WR1_USE,WR2_USE,RD1_USE,RD2_USE: STD_LOGIC_VECTOR (8 DOWNTO 0) ;

SIGNAL RD2 : STD_LOGIC_VECTOR (15 DOWNTO 0);

SIGNAL DRAM0_CS_N,DRAM1_CS_N,DRAM0_DQM,DRAM1_DQM : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"00" ;

SIGNAL DRAM0_A,DRAM1_A : STD_LOGIC_VECTOR(11 DOWNTO 0);

SIGNAL RD2_temp : STD_LOGIC_VECTOR (15 DOWNTO 0);

COMPONENT sdram_pll IS

PORT (

inclk0 : IN STD_LOGIC;

c0 : OUT STD_LOGIC;

c1 : OUT STD_LOGIC;

c2 : OUT STD_LOGIC

);

END COMPONENT;

COMPONENT Sdram_Control_4Port IS

PORT (

--HOST Side

REF_CLK : IN STD_LOGIC; --System Clock

RESET_N : IN STD_LOGIC; --System Reset

CLK : IN STD_LOGIC; --

-- FIFO Write Side 1

WR1_DATA : IN STD_LOGIC_VECTOR (15 DOWNTO 0); --Data input

WR1 : IN STD_LOGIC; --Write Request

WR1_ADDR : IN STD_LOGIC_VECTOR (22 DOWNTO 0); --Write start address

WR1_MAX_ADDR: IN STD_LOGIC_VECTOR (22 DOWNTO 0); --Write max address

WR1_LENGTH : IN STD_LOGIC_VECTOR (8 DOWNTO 0); --Write length

WR1_LOAD : IN STD_LOGIC; --Write register load & fifo clear

WR1_CLK : IN STD_LOGIC; --Write fifo clock

WR1_FULL : OUT STD_LOGIC; --Write fifo full

WR1_USE : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); --Write fifo usedw

-- FIFO Write Side 2

WR2_DATA : IN STD_LOGIC_VECTOR (15 DOWNTO 0); --Data input

WR2 : IN STD_LOGIC; --Write Request

WR2_ADDR : IN STD_LOGIC_VECTOR (22 DOWNTO 0); --Write start address

WR2_MAX_ADDR: IN STD_LOGIC_VECTOR (22 DOWNTO 0); --Write max address

WR2_LENGTH : IN STD_LOGIC_VECTOR (8 DOWNTO 0); --Write length

WR2_LOAD : IN STD_LOGIC; --Write register load & fifo clear

WR2_CLK : IN STD_LOGIC; --Write fifo clock

WR2_FULL : OUT STD_LOGIC; --Write fifo clock

WR2_USE : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); --Write fifo usedw

-- FIFO Read Side 1

RD1_DATA : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); --Data output

RD1 : IN STD_LOGIC; --Read Request

RD1_ADDR : IN STD_LOGIC_VECTOR (22 DOWNTO 0); --Read start address

RD1_MAX_ADDR: IN STD_LOGIC_VECTOR (22 DOWNTO 0); --Read max address

RD1_LENGTH : IN STD_LOGIC_VECTOR (8 DOWNTO 0); --Read length

RD1_LOAD : IN STD_LOGIC; --Read register load & fifo clear

RD1_CLK : IN STD_LOGIC; --Read fifo clock

RD1_EMPTY : OUT STD_LOGIC; --Read fifo empty

RD1_USE : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); --Read fifo usedw

-- FIFO Read Side 2

RD2_DATA : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); --Data output

RD2 : IN STD_LOGIC; --Read Request

RD2_ADDR : IN STD_LOGIC_VECTOR (22 DOWNTO 0); --Read start address

RD2_MAX_ADDR: IN STD_LOGIC_VECTOR (22 DOWNTO 0); --Read max address

RD2_LENGTH : IN STD_LOGIC_VECTOR (8 DOWNTO 0); --Read max address

RD2_LOAD : IN STD_LOGIC; --Read register load & fifo clear

RD2_CLK : IN STD_LOGIC; --Read fifo clock

RD2_EMPTY : OUT STD_LOGIC; --Read fifo empty

RD2_USE : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); --Read fifo usedw

-- SDRAM Side

SA : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); --SDRAM address output

BA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); --SDRAM bank address

CS_N : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); --SDRAM Chip Selects

CKE : OUT STD_LOGIC; --SDRAM clock enable

RAS_N : OUT STD_LOGIC; --SDRAM Row address Strobe

CAS_N : OUT STD_LOGIC; --SDRAM Column address Strobe

WE_N : OUT STD_LOGIC; --SDRAM write enable

DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);--SDRAM data bus

DQM : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) --SDRAM data mask lines

);

END COMPONENT;

BEGIN

u1 : sdram_pll PORT MAP (iCLK_50,sdram_ctrl_clk,oDRAM0_CLK,oDRAM1_CLK);

u2 : Sdram_Control_4Port PORT MAP (iCLK_50,'1',sdram_ctrl_clk,b"0001000100010001",'1',b"00000000000000000000000",b"00101000000000000000000",b"100000000",'1',iCLK_28,WR1_FULL,WR1_USE,

b"0000000000000000",'-',b"00000000000000000000000",b"00000000000000000000000",b"000000000",'0','Z',WR2_FULL,WR2_USE,

oLEDR,'1',b"00000000000000000000000",b"00101000000000000000000",b"100000000",'1',iCLK_28,RD1_EMPTY,RD1_USE,

RD2_temp,'-',b"00000000000000000000000",b"00101000000000000000000",b"100000000",'0','Z',RD2_EMPTY,RD2_USE,

DRAM0_A,oDRAM0_BA,DRAM0_CS_N,oDRAM0_CKE,oDRAM0_RAS_N,oDRAM0_CAS_N,oDRAM0_WE_N,DRAM_DQ,DRAM0_DQM);

oDRAM0_A <= "0"&DRAM0_A;

oDRAM0_CS_N <= '0' WHEN (DRAM0_CS_N = "00") ELSE '1';

oDRAM0_LDQM0<=DRAM0_DQM(0);

oDRAM0_UDQM1<=DRAM0_DQM(1);

oLEDG(0)<=sdram_ctrl_clk;

END ARCHITECTURE;