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Honored Contributor
Honored ContributorUsing Qsys SRAM and SDRAM controllers without a Nios II
I need to communicate with the SRAM in the DE2-115 board using purely VHDL code. No Nios II. Later I may have to use the SDRAM instead if bigge memory is required. I understand that a controlle...
Altera_ForumHonored Contributor
Honored ContributorOK, I have found what the problem is all along. Qsys is not generating the same files when I select VHDL under Generate HDL in "simulation" tab then when I select Verilog. I am going to post a new question. Now makes sense why the information in documentation does not match the software and why ModelSim said that an entity is "not bound". IT IS HAPPENING BECAUSE OF A BUG IN QSYS.
