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Altera_Forum's avatar
Altera_Forum
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9 years ago

Using Qsys SRAM and SDRAM controllers without a Nios II

I need to communicate with the SRAM in the DE2-115 board using purely VHDL code. No Nios II. Later I may have to use the SDRAM instead if bigge memory is required. I understand that a controlle...
Altera_Forum's avatar
Altera_Forum
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9 years ago

I wouldn't classify the SDRAM Controller as an [Megacore-style] "IP Core", and I don't think the instructions you are reading apply. The SDRAM Controller gets generated by a perl script invoked by Qsys with the parameters you have supplied in the Qsys GUI, which creates a plain-text Verilog module with the controller in it. There aren't any parameters you control through HDL, and the controller can only be changed by re-generating the Qsys system.

The controller itself ("just the controller") is sitting in simulation/submodules/blah-blah-blah-new_sdram_controller_0.v or similar filename based on how you have named it. Add that Verilog to your testbench and wire it up, if you care to approach it this way.

For an SDRAM model to wire it to, the ones supplied by Micron were pretty easy to work with.