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corestar's avatar
corestar
Icon for Contributor rankContributor
3 years ago
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Using multiple LVDS ADC in a single Arria 10 GX IO bank

I want to use 8 LTC2271 16-bit ADC in an Arria 10 GX 320. They use serial LVDS and each one needs 4 LVDS pairs (bit clock, frame clock and 2 data lanes). The FPGA has 8 IO banks, so we could clearly ...
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  • FvM's avatar
    FvM
    3 years ago

    Hi,
    it's not generally necessary to connect DCO and FRAME clock of all ADCs. There are different choices to acquire the serial data.

    - use individual DCO and FRAME clock but no RX PLL. At least DCO must use dedicated clock input.

    - use FRAME clock and PLL per ADC, generate bit clock internally. FRAME must use dedicated clock input
    - if delay skew between individual ADC is small enough (e.g. no additional buffers and long traces involved), use common DCO and FRAME clock for all ADC
    - if you are unsure about delay skew but want to avoid individual clock inputs for each ADC, you can use soft CDR with training pattern on startup. Need to connect ADC SPI interface

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,
it's not generally necessary to connect DCO and FRAME clock of all ADCs. There are different choices to acquire the serial data.

- use individual DCO and FRAME clock but no RX PLL. At least DCO must use dedicated clock input.

- use FRAME clock and PLL per ADC, generate bit clock internally. FRAME must use dedicated clock input
- if delay skew between individual ADC is small enough (e.g. no additional buffers and long traces involved), use common DCO and FRAME clock for all ADC
- if you are unsure about delay skew but want to avoid individual clock inputs for each ADC, you can use soft CDR with training pattern on startup. Need to connect ADC SPI interface

  • corestar's avatar
    corestar
    Icon for Contributor rankContributor
    3 years ago

    Hello @FvM

    That's alot to think about.

    Side Note: In the past (using Cyclone V) we did not bother with a FRAME clock at all. Used a test pattern for bit slip and it also gives a nice warm feeling that all the data is coming in correctly.

    Regarding your list:

    - use individual DCO and FRAME clock but no RX PLL. At least DCO must use dedicated clock input.

    Are you saying I don't need a PLL at all?

    - use FRAME clock and PLL per ADC, generate bit clock internally. FRAME must use dedicated clock input

    I'm afraid we don't have enough PLL for that. Unless we can use an fPLL. Does the LVDS serdes care what kind of PLL is used? If not, I could just feed the DCO into an fPLL and put multiple ADC on a bank with no problem.

    - if delay skew between individual ADC is small enough (e.g. no additional buffers and long traces involved), use common DCO and FRAME clock for all ADC

    I'm not sure we can depend on that even if all the traces are the same length. For the LTC2271, we have a DCO of 160 MHz. It outputs the DCO at the center of the data but with significant variation of 0.3 tSER (which 3.25 ns). Almost a ns. Then the tPD between the ENC clock and DCO varies by another 0.8 ns. Seems risky.

    - if you are unsure about delay skew but want to avoid individual clock inputs for each ADC, you can use soft CDR with training pattern on startup. Need to connect ADC SPI interface

    Need to investigate this option more. Looking at Figure 110 in the Arria 10 handbook, it still shows an IOPLL. Are you saying use a single DCO input to drive a PLL that drives more than one ADC (all in same bank)? Then let the DPA pick the right phase for each ADC LVDS lane?

    The LTC2271 centers the DCO on the data very nicely. I had not planned to use DPA (they Cyclone V did not even have it). It seems to me DPA might actually screw things up. There are only DPA 8 clocks 45 degrees apart.

    If I could use an fPLL as an external LVDS PLL, it seems like the whole problem goes away.

    Thanks for the help.