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Altera_Forum's avatar
Altera_Forum
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15 years ago

using fpga output pin as enable

Hi,

I'm trying to use an FPGA output pin (through a pin header) as an enable for a switch.

I've noticed that when the enable is "low", it's voltage is actually around 0.13 V with respect to ground (with nothing else connected). Are there any settings for the pin that I should keep in mind in order to ensure a lower voltage? I have a clock signal that is being input into the same I/O bank and it has a higher drive strength (12mA) -- would that effect this enable signal?

Any pointers are appreciated.

Thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I possibly didn't understand your intention well, but 0.13 V is a pretty good low level related to any possible I/O standard. The residual voltage is most likely caused by internal voltage drops in the FPGA (assuming the output is actually unloaded). It's not intended as as an analog output voltage, however. If you need exactly zero volt, use an analog switch or a CMOS single gate buffer.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    K, thanks for the tip. I tried a stronger drive strength and that brought it down to 0.07 V.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Be careful, there is no guarantee that it will stay that low on all the temperature range. As FvM said, if you want to ensure a low voltage, use an external switch. Don't rely on any adjustable parameter on the FPGA.