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Altera_Forum's avatar
Altera_Forum
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8 years ago

Using Cypress FX3 as device for Passive Serial

Hey, So I'm working on a setup with the Cyclone 3 (specifically EP3C5E144C8N), which uses a Cypress FX3 board as the passive serial initialisation device. Unfortunately I cant seem to get the d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

nSTATUS going low before configuration completes indicates the FPGA has detected an error.

I'm concerned about the relative timing between the clock and data. If you're configuring from such a remote source - by the looks of the FX3 solution it's going to be quite a lot further from the FPGA than ideal - then 25MHz sounds a little punchy to me, regardless of the 133MHz max speed supported by Cyclone III.

What does the relative timing between DCLK and DATA0 look like at the FPGA?

Cheers,

Alex