Altera_Forum
Honored Contributor
12 years agoUse shared pll with serdes without DPA or CDR?
Hello,
I am trying to transmit data via serial connection over the HSMC-Connector using LVDS between to boards (Cyclone IV and Cyclone V-SoC, obviously with different clock sources). Therefore I have on each side an altlvds-tx and an altlvds-rx megafunction. Does it thus make sense to connect the rx and tx pll on each side instead of clocking each receiver by its corresponding transmitter? Without DPA or CDA, I will run into phase shift problems when using shared pll for rx and tx, depending on synchronicity of the clock sources and cable length, am I right? In which cases is it sensible to use shared pll (apart from my case where Quartus cannot place the matching fractional pll when using the HSMC-Connector...)? I am asking this, as I would like to know if I should try further to use different clocks for rx and tx (and to solve the placing issue) or to investigate the possibility of inserting a synchronizing solution. Thanks herrhannes