Use shared pll with serdes without DPA or CDR?

If you can, I suggest sending the respective clocks with the data and clocking the data into the receiving device with that clock. Depending on the respective trace delays between data and clock you may require a PLL at each device's receiver to guarantee setup & hold on the data being clocked into the fabric.

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Does it thus make sense to connect the rx and tx pll on each side instead of clocking each receiver by its corresponding transmitter?

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This implies you'd consider operating the LVDS rx & tx links from the same clock. You're going to have to cross clock domains somewhere. It may make sense to only do this a one end of the link, not both. It could be an acceptable way of operating the link, depending on your system requirements.