Honored Contributor
Honored ContributorIt’s so kind of you to help me settle this matter,which help me generate the IP core successfully.But now I encounter some new troubles.When the IP CORE was generated suscessfully,I choosed the the testbench which was generated by the fir compiler V13.1.I can show you the details.
First picture shows these files in my project https://alteraforum.com/forum/attachment.php?attachmentid=15267&stc=1 which confused me is that the file-"fir_ipcore_make_bb.v" whether it should be included in my design? I remove this file from my project,and use the testbench file-‘tb_fir_ipcore_make’,the simulation tool is Modelsim-altera.when I compile my whole project,it shows the erro in‘tb_ipcore_make’,you can see it in the following picturehttps://alteraforum.com/forum/attachment.php?attachmentid=15270&stc=1 which says"Error (10481): VHDL Use Clause error at tb_fir_ipcore_make.vhd(72): design library "work" does not contain primary unit "fir_ipcore_make"",so I change the primary unit to “fir_ipcore_make_ast”,I don't know it's wrong or right,but it worked,and the compilation was successful. After I finished all of these settings and run the RTL simulatin,it noticed me there were something wrong,just as the second picture showshttps://alteraforum.com/forum/attachment.php?attachmentid=15268&stc=1 I saved this message, here it is Because I’m a beginner in FPGA design，so these things are difficult for me and I want to know what I should do.I am so sorry if I have bothered you. Thank you again. Best regards to you!
