USB3.x LFPS transmission and detection with FPGA transceiver

Based on this published paper, the concept should be similar wrt to LFPS implementation using FPGA
https://arxiv.org/pdf/2301.11505v1

1. LFPS Reception: Does the FPGA transceiver provide any signal to indicate electrical idle state?
Altera FPGA transceivers do provide a signal that can be used to detect the presence or absence of electrical idle. Specifically:
See: https://community.intel.com/t5/FPGA-Wiki/Design-Example-PHY-Interface-for-PCI-Express-PIPE/ta-p/735980
The pipe_rxelecidle signal (or its equivalent depending on the PIPE interface implementation) indicates whether the receiver is in an electrical idle state.
When RXELECIDLE = 0, it implies that LFPS is being received (i.e., the link is active).
When RXELECIDLE = 1, it indicates that the link is in electrical idle, and no LFPS is being received.
This behavior is consistent with USB 3.x PHY expectations, where LFPS detection relies on transitions between idle and active states on the differential lines1.

2. LFPS Transmission: Can LFPS be sent by controlling pipe_txdetectrx and pipe_txelecidle?
Theorectically, LFPS transmission can be achieved by manipulating the transceiver's PIPE interface signals:

To initiate LFPS transmission, the following conditions are typically used:

TXDETECTRX = 1
TXELECIDLE = 1
txpd = 2'b00 and rxpd = 2'b00 (power-down controls)
To wake up a link partner, the conditions change to:

TXELECIDLE = 0
txppd = 2'b01 and rxpd = 2'b01
These control signals directly influence the raw data output of the SerDes block, allowing you to generate LFPS bursts by toggling the differential lines at low frequencies (typically 10–50 MHz square waves)1.

Additionally, LFPS generation can be done in soft logic by bypassing 8b10b encoding and directly driving the transceiver with patterns like 0xFFFFFFFFFF to simulate high-level signals. Timing must be carefully managed to meet USB 3.x LFPS specifications (e.g., tBurst, tPeriod, tRepeat)