USB fT245 max II

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HI, im working with Max II . it has a CPLD and an device usb the FT245, do anybody have worked with that?, i did an example with labview and VHDL, i can communicate with pc, but the signal TXE doesnt work very well,

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What do you mean by "doesn't work well"?

TXE# starts out low, and after you pulse WR, it pulses high for about 500ns. When it goes low again, you can pulse WR again.

This is how it worked on the FT2232C device I was testing (in FT245 mode).

Cheers,

Dave

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but the signal TXE doesnt work very well

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= you didn't yet read the FT245 datasheet?

i have already read all datasheet, the device works with TXE and WR, this is my program

-- usb_ft245.vhd

-- 09/05/011

-- J.C. Hdz De Torres

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY usb_ft245 IS

PORT(

clk : IN STD_LOGIC;---------- contador

data_port: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);

INPUTS: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

OUTPUTS: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

LECTURA: IN STD_LOGIC;

A: IN STD_LOGIC;

RD: OUT STD_LOGIC;

WR: OUT STD_LOGIC;

RXF: IN STD_LOGIC;

TXE: IN STD_LOGIC);

END usb_ft245;

ARCHITECTURE usb_driver OF usb_ft245 IS

SIGNAL data_in : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL data_out : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL read_or_write : STD_LOGIC;

--------señales del contador------------------------

SIGNAL contador_periodo : STD_LOGIC_VECTOR(16 DOWNTO 0);

SIGNAL lectura_signal : STD_LOGIC;

BEGIN

PROCESS

BEGIN

WAIT UNTIL(clk'EVENT) AND (clk='1');

--the antity is ready to send a byte.

--Find out if the ft245 is ready to receive a byte

---IF (LECTURA = '1') THEN

WR <= '0';

IF (TXE = '0') THEN -- to send data from the peripheral to the host

IF (LECTURA = '1') THEN----------------------------------------------------

data_in <= INPUTS; ---carga los datos en e host

data_port <= data_in;

IF(contador_periodo >= 10 AND contador_periodo < 15)

THEN WR <= '1';

ELSE

WR <= '0';

END IF;

--Reset del contador

IF (contador_periodo = (23)) THEN

contador_periodo <= "00000000000000000";

ELSE

contador_periodo <= contador_periodo + 1;

END IF;

else--------------------

data_port<="ZZZZZZZZ";--------------------------

END IF;

END IF;

END PROCESS;

END usb_driver;

but the signal TXE doesnt seem to datasheet , it has something like noise,

the yellow signal is TXE, WR is blue

http://www.alteraforum.com/forum/attachment.php?attachmentid=4552&stc=1&d=1313505805

You need to learn how to use oscilloscope probes correctly.

Your oscilloscope traces show huge amounts of ringing. This is typically due to having a large loop of ground wire in your ground clip. Try using a shorter ground lead, or a probe tip that allows you to probe both the signal and ground with a very small amount of space between them.

Cheers,

Dave

dwh@ovro.caltech.edu (http://www.alteraforum.com/forum/member.php?u=21847) http://www.alteraforum.com/forum//proweb/statusicon/user_online.gif

Altera Guru

dwh@ovro.caltech.edu (http://www.alteraforum.com/forum/member.php?u=21847) http://www.alteraforum.com/forum//proweb/statusicon/user_online.gif

Altera Guru

thanks thanks for your help dwh. Iam using the oscilloscope correctly. actually im probing from the board (MAX II kit develop), but I m not sure about the code, the example USB from kit's cd doesnt run, and the code is building under Verilog, I work with VHDL.

Here's a scope trace of WR and TXE# probe at the pins of the FT245BM on the MAX II PCI development kit. The scope probe was longer than I would normally use; it was clipped to a ground connection in the prototype area. The small amount of ringing seen in the traces is due to the probe ground.

The signal quality of this trace is fine, there is no ringing due to the board layout.

Cheers,

Dave

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could you show me an code example?

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Not at the moment. I was capturing transaction waveforms so that I could build an interface. If you don't mind waiting a few days, I'll probably post some code then.

Cheers,

Dave

I swapped a defective CPLD in a USB blaster to do some experiments with this.

The part is fairly small, so there isn't exactly a lot you can do, but I did end up writing a USB -> SPI bridge. I swapped the oscillator for a 10MHz part (which I had in stock) so I could do every thing in a single clock cycle.

More recently, I built a board with a FT245 and a Cyclone III (3c16), and did a proper bus-attached UART interface for it. This system has a much faster oscillator, and I have to implement counter delays.

I could show the code, but it's fairly straightforward. I have two idle states, and toggle between them unless their check conditions are true. Note that all I/O from the FT245 is registered, to get the signals into the internal clock domain.

In the first IDLE state, I sample RXFn and PWRENn to see if they are both low. If they are, I initiate a read from the external FIFO and copy it to an internal FIFO.

In the second IDLE state, I check the internal transmit FIFO, and if it is not empty, I perform a write to the external FIFO. Obviously, during the write state I have to enable the output drivers.

There is some code to handle the bus turn-around, but functionally this is all that is happening. The internal bus clock is 72MHz, and I have gotten pretty close to the theoretical max data rate for the FT245 using the UART.

I could probably get even closer with careful use of the Send Immediate pin, but so far, I haven't needed to use it.