Forum Discussion
Honored ContributorUSB Blaster VCC
Hello :)
I'd like a quick confirmation about the USB Blaster. I'm implementing my design on a PCB, and I've to make a connector to programm my FPGA with the USB Blaster. So I decided to programm my FPGA with JTAG (is it a good choice? Will I be able to programm my FPGA like this?), made a connector on my PCB, and connected TCK, TDO, TMS, TDI and the two GND according the USB Blaster User guide. But I don't know how to connect VCC: is it the VCC of the IO (in my case: 3.3V), or the VCCint? (So, 1.2V for the cyclone 3...) Thanks in advance, ParalaX14 Replies
Altera_ForumComing back to a previous question:
--- Quote Start --- I am curious if anyone has consistently designed the JTAG header at VCC of 3.3V and had the FPGA successfully program time after time? With or without clamping diodes? --- Quote End --- The 2.5V JTAG supply suggestion has been newly introduced by Altera with Cyclone III, together with a bunch of "Watch your step" statements related to the danger of input overvoltage. Curiously, the overvoltage specification is nearly unchanged between Cyclone II and Cyclone III. The real device overvoltage capability has changed of course with the technology and in so far it's quite reaonable to look more thoroughly on some problems that existed since long. Overshoot of JTAG signals is mainly a matter of reasonable termination respectively transmission line impedance design, so you can achieve non-overshoot JTAG signals. As already discussed, clamp diodes are also an effective way. But a vendor suggestion need to consider different programming hardware, modified JTAG cables and different board routing. So I understand, why Altera promotes 2.5 V JTAG. It's your decision to follow or ignore the suggestion. Most JTAG circuits designed by my customers or myself are still using 3.3V. Only part of it (mostly industrial boards) is utilizing clamp diodes.- Altera_Forum--- Quote Start --- Dave, the schematic that you provided a link to is most interesting . . . so the 100 ohm buffer's in Dave's schematic provide the resistive damping in the equivalent RLC circuit that would exist on the PCB between the JTAG pins and the FPGA itself . . . buffered of course. I like it. This limits the energy going into the FPGA pins that are JTAG, which are basically designated as 2.5V for truly safe operation . . --- Quote End --- The resistor can be used for several purposes; 1) The traces are nominally source terminated transmission lines. The ideal resistance for a source termination is that it plus the driver output impedance match the transmission line impedance (typically 50-Ohms or 65-ohms depending on the trace and PCB geometry). 2) You can use it to slow down the rise-time of the buffer output; the R acts with the C load (the trace and the capacitance of the end pad). 3) Its a debug feature; you can start lifting resistors to remove components from the JTAG chain. I've had cases where an FPGA is dead. I can jumper over it, check everything else is working, and then get the FPGA removed. The placement of the board was reviewed with the assembly company (SigmaTron) to ensure the board could be reworked. --- Quote Start --- I have thought for a long time to make a small board that would be a JTAG adapter. It would have a CPLD on it, that would take in multiple types of JTAG cables (Altera and Terasic/Altera clones, for example) and then provide the appropriate target board JTAG signals, whether the target board be at 100 mil pitch, 50 mil pitch, etc. What you have done is very similar to this, but located on the board itself, and with digital logic rather than a CPLD. --- Quote End --- The problem with this type of board is that there is no generic hook into the Altera software. To make a general purpose board, you need to have your adapter be able to fool Quartus into thinking it is communicating with a USB Blaster. That information is not provided by Altera, however, there is enough information on the internet to build your own FT245+CPLD or Cypress FX2 USB-Blaster. Its an interesting challenge :) Cheers, Dave
- Altera_Forum
Dave and Daixiwen; Thank you for your comments. Dave, the schematic that you provided a link to is most interesting . . . so the 100 ohm buffer's in Dave's schematic provide the resistive damping in the equivalent RLC circuit that would exist on the PCB between the JTAG pins and the FPGA itself . . . buffered of course. I like it. This limits the energy going into the FPGA pins that are JTAG, which are basically designated as 2.5V for truly safe operation . .
I have thought for a long time to make a small board that would be a JTAG adapter. It would have a CPLD on it, that would take in multiple types of JTAG cables (Altera and Terasic/Altera clones, for example) and then provide the appropriate target board JTAG signals, whether the target board be at 100 mil pitch, 50 mil pitch, etc. What you have done is very similar to this, but located on the board itself, and with digital logic rather than a CPLD. Thanks! James - Altera_Forum
I use a very similar design, with 74LVCs powered at 3.3V (because this is the Vccio of my bank# 1), and 33 Ohm resistors in series. I have other components in the JTAG chain, and the possibility to move resistors to exclude them from the chain and have only the FPGA (yes, I don't trust the Quartus programmer that much :D ).
You must be sure that the buffers you use are fast enough for the Jtag signals. - Altera_Forum
Hey James,
Here's a design with lots of JTAG buffers/tricks in it, feel free to ask questions; http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf Page 7 has a high-level overview. Look on the front page for the other locations of JTAG stuff, eg., page 44, 77, 78, 79. Some of the FPGA outputs are 2.5V, and they're run into 3.3V buffers, mainly so that the LEDs are on bright enough. The TinyLogic buffers are cheap and convenient to place and route on a PCB. Cheers, Dave - Altera_Forum
Daixiwen; That is quite interesting. Are the output of the buffers at 3.3V? Did you put any series resistance in between the buffer and the FPGA? What type of bugger did you use, a standard type 244 or similar? Thanks, James
- Altera_Forum
I'm using 3.3V but I'm using buffers between the JTAG header and the FPGA pins, and no clamping diodes since the buffer is quite close to the FPGA.
- Altera_Forum
I recently had a board (just this week) where I had 3.3V hooked up to VCC pin on the JTAG header for a PCB. The JTAG header was for programming the EP3C5 part and EPCS16 through indirect jtag configuration. The 3.3V on the VCC pin of the JTAG header was a mistake in the schematic that propagated to the PCB. However, since the board had controlled impedance & stackup, I thought I would go ahead and try to make the board work. The FPGA programmed about 3 times, then after that, it quit. I could recognize the FPGA through the JTAG pins in the Quartus programmer, but could not program it. I've put 2.5V on all JTAG VCC header pins before this, and indeed this PCB issue confirms that 2.5 is essential. I know that you can use clamping diodes if you use 3.3V, but this seems to be extra components when simply using 2.5V will work. I am curious if anyone has consistently designed the JTAG header at VCC of 3.3V and had the FPGA successfully program time after time? With or without clamping diodes?
- Altera_Forum
ParalaX;
I know that you mentioned that you just have a development board. However, in the future, if you want to be able to program both the FPGA and a Flash chip such as an EPCS16, where you have the combined programming of both (using jtag indirect configuration file .jic) then you will want to make sure to have the JTAG header VCC at 2.5 V. -James - Altera_Forum
Thanks a lot to everyone for your informations!
I'll see if I can do AS and JTAG on my board (since I don't have much room for it), but otherwise I'll juste use JTAG and reprogram the FPGA every time. It's no big deal since it's a development board :) ParalaX
