Forum Discussion
2 Replies
- Altera_Forum
Honored Contributor
Do you run it twice in a row from the same software, do you re-upload a new software between the two tests, or are you reconfiguring the FPGA and upload the software between the two tests?
You should put some Signaltap probes on the DMA's master to see if anything different is happening during the tests. - Altera_Forum
Honored Contributor
Yeah, it is correct now. I did a mistake by adding some function in DMA part. Thanks!