Unnecessary long routing path creates timing issues

I'm using the same component in two different designs.

On one of them it passes the timing the timing requirements, but not on the other.

If I look in the details I can see that the failing design is using a CLKCTRL component far away from the design, causing a long clock delay.

But the passing design has chosen a CLKCTRL very close to the IO pins used by my component.

So why does this happen and is there anything I can do about it?

The CLKCTRL close to the IO pins is not used by any other component.

There is no resource issues that I can see, only using 34% of the resources.

I did try Logic Lock, which resulted in the exact same routing and passing timing criterias as the first design, but I want to avoid using logic lock.

I have attached 3 screenshots from chip planner that shows the routing for the 3 scenarios.

I'm using Cyclone V 5CSEMA5F31C6

Thanks / Joakim