uniphy based ddr3 controller and pin_assignments.tcl

Hi,

I am using megawizard flow to create a uniphy based ddr3 controller. I have two instances of the ddr3 controllers. So I created two different cores and instantiated it in two different wrappers. I know in the documentation it says the same scripts will pickup multiple instances of the cores but I am running a test with two cores because of two reasons -

1. It is likely that we may run the two cores at different frequencies.

2. Due to some weird interaction between various wizard generated timing scripts we have to delete the databases before every compile. Otherwise the timing analyzer throws up a warning that it cannot find *read_data_out* keepers. This warning always results in a calibration failure on the board. The SR on Altera's website recommended that we delete the database. Ofcourse, this jacks up our compile times to 1.5 hours. We have 3 instances of serialite, 2 instaces of ddr3 cores and a 10G xaui interface.

So coming back to the problem - I now have two different wizard generated cores but when I run the <core instance name>_pin_assignments.tcl it gives me an error -

Error: Evaluation of Tcl script C:/fpga/syn/ddr3_bot_core_p0_pin_assignments.tcl unsuccessful

Any help would be appreciated.

Thanks.

Sanjay