New Contributor
Regular ContributorHi sovad,
From the schematic, this looks like a power-down fast discharge circuit. When the power enable signal is turned off, the MOSFETs are enabled and the related FPGA power rails are discharged to GND through low-value resistors.
The purpose is to remove remaining voltage on the rails faster after power-off. This can help avoid leftover voltage, slow power-down, quick power-cycle issues, or possible back-powering through other devices.
This is mainly a board-level power design choice and is not a general mandatory requirement for all Altera FPGA designs. It depends on the power design, regulator behavior, rail capacitance, and sequencing needs.
For the exact reason this was added on the Terasic DE10 board, please check with Terasic, as this is part of their board implementation.
