Honored ContributorHello sir,
I want to place a DDR SDRAM (MT46V64M8 – 16 Meg x 8 x 4 banks) with cyclone IV E (ep4ce55f23i7) device. On doing the Early Pin Planning of DDR with this device I am getting warning of Unconstrained output ports under TimeQuest Timing analysis. What can be the probable reason of this warning? How can I remove this warning? Can we ignore this warning?
Honored ContributorSimple Problem: Your Output-Ports are unconstrained (somehow obvious).
Generate a SDC-File containing the constraints like "set_max_skew" and so on to tell the fitter how to handle the signals and to tell TimeQuest how to analyze them. To ignore this warning is possible but may end in an not working design because of massive skew between the parallel signals. This is why you should tell quartus which signals belong to the bus and how much skew, delay and so on is acceptable. The fitter then tries to keep the signals together.
