Unable to write on SDRAM on DE0- Nano Cyclone IV E - waitrequest

Hi,

I have a problem on a project on De0-Nano eval board (Cyclone IV E).

I have no idea where look or what I'm wrong.

I design a system made by: a I2S receiver connected to a fifo and the fifo to a Master Avalon-MM (Qsys System).

The strange behaviour is: I cannot write on SDRAM when I use the signals generated by I2S signals instead works correctly with the below piece of VHDL

	process(clk, rstN)
		variable cnt : integer range 0 to 255 := 0;
	begin
		if (rstN = '0') then
			count <= (others => '0');
			ready <= '0';
						
		elsif rising_edge(clk) then
			if count =  0 then				
				ready <= '1';
				left_channel_in 	<= x"1234" & std_logic_vector ( to_unsigned( cnt, 16)  );
				right_channel_in 	<= x"ABCD" & std_logic_vector ( to_unsigned( cnt, 16)  );
				cnt := cnt +1;
			else
				ready <= '0';
			end if;
			
			count <= count + 1;
			
			
		end if;
	end process;

Below, the signals on avalon bus, in the case of usage of above vhdl

http://www.alteraforum.com/forum/attachment.php?attachmentid=11997&stc=1

If I connect the I2S Reciever to rest of system, it doesn't work, see the image (the waitrequest after the first write never goes low)

http://www.alteraforum.com/forum/attachment.php?attachmentid=11998&stc=1

I don't understand why : in both tests the code which manages the SDRAM is the same and I write in both case to a fifo.

Has Anyone an idea?