Forum Discussion
Altera_Forum
Honored Contributor
10 years agoHi,
The simulation plots you attached are so tiny it's impossible to read them. Good idea to diff the compilation output, I wish I had thought of doing that before, Quartus generates so much output. I also diffed the files and I see two other differences besides the timing issues: ko.txt: Warning (10036): Verilog HDL or VHDL warning at de0_nano.vhd(378): object "step" assigned a value but never read ok.txt: Warning (10036): Verilog HDL or VHDL warning at de0_nano.vhd(320): object "i2s_rx_data_valid" assigned a value but never read That warning about i2s_rx_data_valid never being assigned a value sounds fishy to me.