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Altera_Forum
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10 years ago

Unable to write on SDRAM on DE0- Nano Cyclone IV E - waitrequest

Hi, I have a problem on a project on De0-Nano eval board (Cyclone IV E). I have no idea where look or what I'm wrong. I design a system made by: a I2S receiver connected to a fifo and th...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Hi,

those warnings are caused by two different configuration of the system (KO and OK): in one case (KO) I use "i2s_rx_data_valid" in the other "OK" the signal step.

In any case I decided to clean this and bring the qsys system on top-level module: the funny thing is now seems to work (I'll post the whole system code) but I'm really afraid because this means (maybe, I'm investigating) a change in place&route makes the design not working.

One interesting result: the TimeQuest Analyzer report only 1 "Worst-Case Slack" on clock signal to SDRAM, but I'm not able to evaluate this report and if I have to do anything.

https://www.alteraforum.com/forum/attachment.php?attachmentid=12003