GDagi1
Occasional Contributor
Occasional ContributorUnable to Infer M9K in Quartus
Hi all,
I borrowed some code from a Xilinx project, where RAM was inferred successfully. I would like to do the same in my Quartus 18.1 project with my MAX10 FPGA DevKit. Here's both methods of in...
Your code for the memory block itself is way too complicated for Quartus to infer it from block rams.
You need to look at the verilog templates that Quartus supplies for inferred memory.
Here is what I use and it infers as block ram (M9K, M4K depending) just fine.
Note addr, mdi, mwr are wire type; mdo are reg type.
reg [0:11] memory [0:MEMSIZE-1] /* synthesis ramstyle = "no_rw_check" */;
always @(posedge clk)
begin
if (mwr) memory[addr] <= #TPD mdi;
mdo <= #TPD memory[addr];
end
