Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHi,
1. Are you using Dev Kit? 2. How many devices are there in your JTAG chain? OR Are you programming to the correct device in the chain? Cross check the steps followed for generating the .Jic file. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an370.pdf if the .sof file can be configured via jtag successfully then it is not a power issue since jtag configuration is successful.then it should be bitstream corruption. Suggestion 1. Monitor nStatus & CONF_DONE pins. 2. Try to program with .pof after loading the sfl image. Or check if you have selected correct EPCQ device. 3. Check the P/N from the board and confirm. Refer below link for troubleshooting. https://www.altera.com/support/support-resources/support-centers/devices/cfg-index/fpga-configuration-troubleshooter.html Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)