UART received characters not displaying in the serial monitor

Hi Tex,

Can you be more specific on what are the input and output (serial monitor)? Where are them connected to the Max 10 board?

Thanks,

Best Regards,

Sheng

Hi Tex,

Or how about using UART RS232 IP in embedded Nios system check this design example link https://www.intel.com/content/www/us/en/design-example/715139/cyclone-v-uart-rs-232-maximum-baud-rate-reference-design.html

https://www.intel.com/content/dam/altera-www/global/en_US/uploads/6/64/MAX_BAUD_RATE_CYCLONE_V_SOC_DESIGN_EXAMPLE.pdf

This design contains Clock Source, UART RS232, Nios II Processor, OCRAM and jtag uart. You can choose to use one UART RS232 instead of two. The qsys system you can generate in VHDL if you want. I had successfully implemented this design before with bluetooth module in both Max 10 and Cyclone V. There'll be only 4 ports needed to be assign pin locations:

uart u0 (

.clk_clk (CLK_50), // clk.clk

.reset_reset_n (CPU_RESET), // reset.reset_n

.uart_0_external_connection_rxd (RX0), // uart_0_external_connection.rxd

.uart_0_external_connection_txd (TX0), // .txd

I assign both uart_0_external_connection_rxd and uart_0_external_connection_txd to the Max 10 GPIO pins as UART RXD and UART TXD. Make sure UART RXD is connected to FTDI TXD and UART TXD is connected to FTDI RXD. Also, make sure the UART baud rate matching with the FTDI baud rate.

Then, you have to program the .sof file. After program the .sof file, you have to program the .elf file which is generated after building c code in Eclipse software. The c code is inside the design example software folder.

Thanks,

Best Regards,

Sheng

hi sheng,

I can't able to find any program in the above link please kindly Hewpp me..

any easy one specifically in VHDL pleasee

Hi Tex,

In the link provided, you have to download the .par file. And then open the .par file with Quartus Tool.

Thanks,

Sheng

I understood few things in that thank you sheng

i have moved for an advanced task for myself

Best regards,

Tex