UART peripheral in platform designer as FPGA configured

Hi snehal_p,

I will try to find if there is any example code to your question.

Thanks.

Regards,

Aik Eu

Hi snehal_p,

I have try to find and consult the team for your request.

However there is no example code for your request.

Thanks.

Regards,

Aik Eu

Hi snehal_p,

I will close this thread if no further question.

Thanks.

Regards,

Aik Eu

Hi,

Please refer to the Cyclone V SoC HPS TRM and the following links for reference, we are unable to help you further on the issue:

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/using-unassigned-io-as-loanio.html

https://www.intel.sg/content/www/xa/en/support/programmable/articles/000079307.html

https://www.youtube.com/watch?v=cRwzmsJ1Jkg&ab_channel=IntelFPGA

I hope you are satisfied with our support, pardon us for any inconvenience or any lack of support from our side. I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.