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snehal_p's avatar
snehal_p
Icon for Contributor rankContributor
3 years ago

UART peripheral in platform designer as FPGA configured

Hello, I'm using Cyclone V SOC. Can you please me with example code in which UART hps peripheral is configured as FPGA. PFA screenshot of the platform designer. Thanks, Sneha...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Please refer to the Cyclone V SoC HPS TRM and the following links for reference, we are unable to help you further on the issue:

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/using-unassigned-io-as-loanio.html

https://www.intel.sg/content/www/xa/en/support/programmable/articles/000079307.html

https://www.youtube.com/watch?v=cRwzmsJ1Jkg&ab_channel=IntelFPGA



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