Honored ContributorHi All,
When I run the bridge_enable_handoff command (run bridge_enable_handoff), I receive the following:# # Starting application at 0x3FF79720 ...# # Application terminated, rc = 0x0 The FPGA is programmed and works. What's wrong? Thank you!
Honored ContributorWhen I run printenv bridge_enable_handoff, I'm receiving the following:
bridge_enable_handoff=mw $fpgaintf ${fpgaintf_handoff}; go $fpga2sdram_apply; mw $fpga2sdram ${fpga2sdram_handoff}; mw $axibridge ${axibridge_handoff}; mw $l3remap ${l3remap_handoff} The "application terminated, rc = 0x0" occurs when I run the 'go $fpga2sdram_apply' command. So, how to fix? Actually I want to make the read/write accesses to/from AXI3 lightweight bridge.Honored Contributoreverythings seems to be okay.
If you are unable to access the bridge (lwhps2fpga) you may need to build a new preloader or set the axibridge_handoff by hand before freeing the bridges, but after programming the fpga.Honored Contributor1) "need to build a new preloader" - what should the preloader include?
2) "set the axibridge_handoff by hand before freeing the bridges" - how should I do so? what commands to run? 3) while building the preloader, is it possible to add more u-boot commands (like unix-like 'grep', 'which',etc.)?Honored ContributorThe axibridge_handoff is set to 0x00000005... What should it represent?
Honored ContributorHi,
you may want to read some articles at [1] to get knowledge about the bridges and maybe a sample workflow for the Altera SoC?! [1] www.rocketboards.orgHonored Contributormaybe also refer to a bridge usage like Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU.tar ?
Honored ContributorUnfortunately I'm not an Embedded Engineer, just a FPGA Engineer... Will look through the referenced by you docs, thank you!
Honored Contributorthe implementation of the bridge is done by programming algorithm. Where all the bridges is just a hardware resources that allow the software to manipulate the data transfer.
