Altera_ForumHonored Contributor8 years agoTSE & PHY configuration problem Hello there, I have an issue of using TSE on Arria 10 SoC board. I build the Ethernet system with internal loopback and all processes seem correct and perfectly work. my issue is that connectio...Show More
Altera_ForumHonored Contributor8 years agoYeah, you are totally right. How I missed this point! Thank you very much, my friend.
Recent DiscussionsLooking for the Document ID 854068SolvedAbout floating voltage of the Agilex 3 power on resetSuggestion of carry chain type TDC of Cyclone 10 GX FPGA chipsIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAImplementation of lower data rate.