Altera_Forum
Honored Contributor
13 years agoTrying to make sense of this always block
Hi,
So I wanted to take an input and decrement it in a combinational block.. here is the code I am talking about..always @ (posedge clock or posedge reset)
begin
if (reset)
begin
t0_reg <= 0;
t1_reg <= 20'd1;
n <= i;
end
else
begin
t0_reg <= t0_next;
t1_reg <= t1_next;
n <= n_next;
end
end
always @ (*)
begin
t0_next = t0_reg;
t1_next = t1_reg;
n_next = i;
if(n == 0) t0_next = 0;
else
begin
t1_next = t0_reg + t1_reg;
t0_next = t1_reg;
n_next = n - 1;
end
end here i is a 4 bit input.. This circuit is for a fibonacci series.. When I made this I did not think this would work, because I thought at the end of the always @ * block the n_next signal would have been decremented by 1, but at the start of the same block it would again be assigned the value of i.. but what really happens is i keeps decrementing till it reaches 0.. and after it reaches 0 it gets the original value of i again and keeps going forever like this.. isnt this block read from top to bottom.. why does it appear that it stays in the else block till it decrements n_next to 0? Thanks