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Altera_Forum
Honored Contributor
Honored ContributorTrying to make sense of this always block
Hi, So I wanted to take an input and decrement it in a combinational block.. here is the code I am talking about.. always @ (posedge clock or posedge reset)
begin
if (reset)
...
Altera_ForumHonored Contributor
Honored ContributorThe behavior you mentioned is what I would expect... I think I never write combinational code in always statements like that. To me this would be much easier to understand ....
assign t1_next = (n == 0)? 0 : (t0_reg + t1_reg); assign t0_next = (n == 0)? t0_reg : t1_reg; assign n_next = (n == 0)? n : n - 1; If you are not familar with the terinary operator this is what it means: assign signal = (conditional)? true statement : false statement; So above when n equals 0 the statement before the colon is used, otherwise the statement after the colon is used (2:1 mux). If you use something with more statements then I recommend using case statements instead to implement the mux since a casescade of terinary operators uses priority (unless that's what you want).
