Trouble interfacing FLASH pins to GPIO (retro game related)

--- Quote Start ---

You have to create a SIGNAL assignment for an additional signal in the design.

SIGNAL FL_ADDR_TEMP (21 DOWNTO 0);

Then let's say you want to access address location 0x24ffff (22 bit wide address though your code isn't using any of the upper bits for some reason):

FL_ADDR <= x"24ffff";

FL_ADDR_TEMP <= FL_ADDR;

Then the code you have would be:

GPIO_0(2) <= FL_ADDR_TEMP(17);

GPIO_0(24) <= FL_ADDR_TEMP(16);

GPIO_0(4) <= FL_ADDR_TEMP(15);

GPIO_0(29) <= FL_ADDR_TEMP(14);

GPIO_0(28) <= FL_ADDR_TEMP(13);

GPIO_0(5) <= FL_ADDR_TEMP(12);

GPIO_0(25) <= FL_ADDR_TEMP(11);

GPIO_0(23) <= FL_ADDR_TEMP(10);

GPIO_0(26) <= FL_ADDR_TEMP(9);

GPIO_0(27) <= FL_ADDR_TEMP(8);

GPIO_0(6) <= FL_ADDR_TEMP(7);

GPIO_0(7) <= FL_ADDR_TEMP(6);

GPIO_0(8) <= FL_ADDR_TEMP(5);

GPIO_0(9) <= FL_ADDR_TEMP(4);

GPIO_0(10) <= FL_ADDR_TEMP(3);

GPIO_0(11) <= FL_ADDR_TEMP(2);

GPIO_0(12) <= FL_ADDR_TEMP(1);

GPIO_0(13) <= FL_ADDR_TEMP(0);

--- Quote End ---

Ok, so I have re-written my code to hopefully make things more clear. I have changed the data bus behavior to work as "read-only" from the Flash chip, so that should make things simpler to implement. However, this still isn't working:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mapper_test is
	port( 
	FL_ADDR  	: out   std_logic_vector(21 downto 0);
	FL_DQ    	: in    std_logic_vector(7 downto 0);
	FL_CE_N  	: out   std_logic;
	FL_OE_N  	: out   std_logic;
	FL_RST_N 	: out   std_logic;  
	FL_WE_N  	: out   std_logic; 
--	LEDR     	: out   std_logic_vector(9 downto 0);    
--	LEDG     	: out   std_logic_vector(7 downto 0); 
--	SW       	: in    std_logic_vector(2 downto 0);
	
	SNES_ADDR   : in 	  std_logic_vector(21 downto 0);  -- SNES ADDRESS BUS
	SNES_DATA	: out   std_logic_vector(7 downto 0); 	 -- SNES DATA BUS
	SNES_ROMSEL : in    std_logic; 							 -- /ROMSEL (CART PIN 49)
	SNES_RST		: in    std_logic; 							 -- CART RESET
	SNES_VCC    : in    std_logic; 							 -- CART VCC
	SNES_RD		: in    std_logic 							 -- SNES /RD
	
	);
	
end mapper_test;
architecture arch of mapper_test is
begin
	--FLASH CONTROL PINS
	FL_CE_N <= SNES_ROMSEL; 									 -- INPUT SNES /ROMSEL TO OUTPUT FLASH /CE
	FL_OE_N <= SNES_RD;  									    -- INPUT SNES /RD TO OUTPUT FLASH /OE
	FL_RST_N <= '1'; 												 -- KEEP FLASH /RST HIGH
	FL_WE_N  <= '1'; 												 -- KEEP FLASH /WE HIGH
	
	--FLASH DATA PINS
	
	SNES_DATA(7 downto 0) <= FL_DQ(7 downto 0); 			 -- INPUT FLASH DATA BUS (7:0) TO OUTPUT SNES DATA BUS (7:0) FOR READ MODE
	
	--ADDRESS PINS
	FL_ADDR(14 downto 0) <= SNES_ADDR(14 downto 0);		 -- INPUT SNES ADDRESS (14:0) TO OUTPUT FLASH ADDRESS (14:0) 
	FL_ADDR(20 downto 15) <= SNES_ADDR(21 downto 16); 	 -- LOROM CONFIG ---> INPUT SNES ADDRESS (21:16) TO OUTPUT FLASH ADDRESS (20:15)
	FL_ADDR(21) <= '0';											 -- KEEP FLASH(21) LOW FOR 2MBYTE ONLY
	
	
	end arch;

Any ideas of what else it could be? I figure it still has to be with the data bus, but I don't know how else to write it.