Honored Contributor
Honored ContributorI can't tell from the screenshot since it's really blury but it looks like you are exporting the Avalon-MM slave ports of the F2S interfaces so are you making sure to adhere to the Avalon-MM specification in your logic hooked up to those ports? For example, when the port is setup for Avalon-MM there is a 8-bit burst signal but if you don't adhere to the spec you could end up posting an unsupported burst size (8-bit burst signal means you can only post burst of 1-128). Normally I tell users to just simulate their system because things like that will be caught through assertion statements but since your masters are integrated outside of Qsys that won't be the case.
Other things to watch out for is that once you assert read or write you must keep it asserted until the transaction completes. Completion of a transaction occurs on the last beat of the burst when read/write is high and waitrequest is low. I could keep rambling on but if you haven't already done so I would review the rules in the Avalon-MM specification. I doubt your split enviornment is causing this unless you are mixing tools versions.
