Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Triple Speed Ethernet (TSE) Performance

Hi,

we are currently developing a system for a data logger. we are using Cyclone III FPGA to log the data from various sensors and store it on a memory. we are also using 10Mbps Ethernet to download the data. as we log over 25GB of data each time, the download process takes long time. after careful investigation, we found out that 10Mbps Ethernet is the bottleneck. we already have triple speed Ethernet IP core and we want to start implementing that. I just want to know that about TSE performance. I know that TSE performance depends on many parameters. however, any comments regarding that is much much appreciated. lets say we buffer 100MB of data in DDR Ram and we want to send it over the Ethernet. what sort of speed we are expecting from that? it is important for us to know the performance at this stage.if we decide to go for it we end up changing hardware and maybe have to go for bigger Cyclone III.

we might get a new dev board and try the design on that.

:)

Many thanks in advance.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The bottleneck on a Nios/TSE system is the TCP/IP stack. The TSE itself can be very fast and use a link at close to 100%, the SGDMA can be quite fast too, but the TCP/IP stack takes a lot of time to process each packet and this will determine the effective bandwidth.

    The actual rate you can acheive depends a lot on your system, what's around it and what the CPU is doing, but with careful optimizations, something in the 50-80 MBits/s should be achievable (don't take my word for it though, test it!).

    I'd definitely recommend to get a dev board and try. Any cheap board with the Marvel PHY chip will do.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Many thanks for your comments. Even 50-Bits/s is fast enough for our application and would be massive improvement. we will get a dev board and will try it. I will let you know the outcome.

    thanks
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    If you use an 'hardware accelerated' UDP transmission you can go up to (and over) 100 MBytes/sec!

    You just program an SGDMA (or mSGDMA) to feed the hardware UDP block (about 1000 LE and 2 M9K), easy peasy as Jamie Oliver would say :)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The first optimization to do is to compile the project with -O3. You'll see a big increase. Then the next one is to use dedicated on board memory for the packet data, as described in an440 (http://www.altera.com/literature/an/an440.pdf). Of course you would need a FPGA with enough on board memory.

    As Josyb says the next step to get more performance is to use hardware to generate the packets, but it's a bit more complicated to set up and is limited to UDP.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for the comments. I have many clues right now to carry on!!!