Triple Speed Ethernet (TSE) MAC without/built-in PHY

Hi,

I realize this is an old thread, but this discussion is about my question so I do not see any reason to create a new thread with the same subject.

Basically, my question has already been asked, but I do not think there is given a clear answer, so I thought I would give it a try again.

scenario:

I am planning to use two Altera Cyclone V GX FPGAs, which I would like to communicate via Ethernet. The two FPGAs are going to be placed on the same board.

I want to use the Triple-Speed Ethernet IP core, and I would like to use a SGMII interface. This means I plan to use the following configuration:

https://www.alteraforum.com/forum/attachment.php?attachmentid=7304

question:

In most scenarios that I have seen the SGMII interface interfaces to a PHY (with a SGMII interface), or in other cases the communication is MAC-to-PHY (without the PCS and PMA).

From what I understand, the PHY provides a feature called auto-negotiation among other things.

however, since i am using a point-to-point connection between two fpgas is it not possible to hard-code information like link-speed, half/full duplex mode and etc., which otherwise would be exchanged and set in accordance to the auto-negotiation? so, i am asking the same question again, does anyone know/has anyone tried to see if it is possible to have a mac-to-mac communication, if used in a point-to-point connection between two fpgas on the same board?

The reason I do not want to use a PHY is the fact that a PHY consumes a lot of power and I do not need to communicate with an optical or copper platform.

Finally, I want to use the SGMII interface, because of its low power, low pin count and differential pair for data and clock.

Thank you in advance,