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Altera_Forum's avatar
Altera_Forum
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15 years ago

Transportation delay problem

Dear Experts,

I am having problem with simulation of the transportation delay,.i.e., it does not show any impact on the resulting waveform.I am using Quartus II

here is the code,copy-pasted from the book.

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY del IS

PORT ( a : IN std_logic;

b : OUT std_logic);

END del;

ARCHITECTURE buf OF del IS

BEGIN

b <= a AFTER 20 ns;

END buf;

THANK YOU,

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    it does not show any impact on the resulting waveform

    --- Quote End ---

    Yes, VHDL and Verilog transport delays are only supported by simulators as ModelSim but not for logic synthesis. Their purpose is e.g. the simulation of logic gate and cable delays. Possibly your book doesn't clearly explain this limitation. The reason for it is simple: In synthesized logic, exact delays can be only implemented by counting clock cycles.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    The reason for it is simple: In synthesized logic, exact delays can be only implemented by counting clock cycles.

    --- Quote End ---

    Thank you for you respond,

    Can you please help me with obtaining the required delay, JUST AS WRITTEN ON THE CODE.

    p.s. I have access only to Quartus II.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    This is not possible.

    The delays depend on the logic, the temperature, the device you chose...

    They will not be the real ones.

    You can simulate the RTL code with ModelSim and see the delays.

    A free limited version of Modelsim can be installed with QuartusII.

    Which version of Quartus are you using?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Which version of Quartus are you using?

    --- Quote End ---

    I am using Quartus II 9.1. Sorry I did not notice. There is a Model Sim Altera Starter Edition 6.4a installed on my computer.

    I was involved on the student project "FPGA based Calculator". We solved the problem by schematic design using D-FFs.However our aim is to develop a VHDL code for it.

    What advice can you give?

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Translate your schematic circuit in VHDL.

    For the moment just take advice from a VHDL book and translate each FF, each adder and each combinatorial block in VHDL code as suggested in the book.

    You can also start with small blocks that in Quartus can be converted in symbols to replace part of your working schematic design.

    Then start using vectors and procedural blocks to improve code readability.

    Always remember that VHDL describes circuits.