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Altera_Forum
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12 years ago

transfer VHDL bi-ports to Verilog bi-ports

Hi! I have been working on transfering a VHDL file to a verilog one. Bidirectional port of D didn't work well... This VHDL file can work on CPLD while the verilog file cann't... PS:Formalit...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Why do you think that the problem is related to bidirectional pin implementation? The coding of this design detail seems equivalent at first sight. As an obvious difference, the state machine is encoded with default one-hot style in Verilog, while it's binary (user) encoded in VHDL. According to the file comments, the binary encoding is required.

Please consider that Altera synthesis attributes can't be translated by X-HDL.

Generally, you would set up a test bench and find out in simulation what goes wrong in Verilog conversion.