New ContributorHi,
For implementation fo QSYS to hard IP of cyclone IV,
You may refer to the user guide.
Let me know if anything is not clear or you need more information about it.
Regards,
Wincent_Intel
Regular ContributorHi,
Glad that it is able to help, Hence I will proceed to close this ticket
Hence, This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread. Thank you
If you feel your support experience was less than a 9 or 10,
please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.
Regards,
Wincent_Intel
New ContributorHi Wincent,
How can I ask for further support on this? Should I open a new ticket?
My customer is wanting to move forward with Cyclone IV GX devices. The UG you sent is for Cyclone V. Is this applicable to the Cyclone IV? I found the user guide the IP Compiler for PCIE User guide which I believe will support the Cyclone IV. With that I could really use and example design to share with the customer. I was unable to find one supported in V18.1 lite
Thanks
