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MiguelAvina's avatar
MiguelAvina
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Transciever Support Cyclone IV - How to implement the PCIE hard IP for Cyclone IV GX

Hi, Is there example code and IP that they we can implement in QSYS for PCIE hard IP for Cyclone IV GX ? Thanks
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Glad that it is able to help, Hence I will proceed to close this ticket


Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you


If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel


  • MiguelAvina's avatar
    MiguelAvina
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Wincent,

    How can I ask for further support on this? Should I open a new ticket?

    My customer is wanting to move forward with Cyclone IV GX devices. The UG you sent is for Cyclone V. Is this applicable to the Cyclone IV? I found the user guide the IP Compiler for PCIE User guide which I believe will support the Cyclone IV. With that I could really use and example design to share with the customer. I was unable to find one supported in V18.1 lite

    Thanks