Hi, I've recently purchased a Stratix V GX Transceiver Signal Integrity Development Kit and I want to use it to transmit and receive data at 10 Gbps so I can study how our optical circuit affects the BER. To this end I've downloaded the Transceiver Toolkit Design Examples from the 'On-chip Debugging Design Examples' webpage. I want to implement the one in the 'sv_1ch_40b_10312mbps' folder, but I ran into some problems. Firstly the example is for a 5SGTC7 device, and my device is 5SGXA7. But the AN644 document (Migration Between Stratix V GX and Stratix V GT Devices) has led me to believe that I can safely migrate the design just by changing the device name and recompiling. After I programmed the board and loaded the design in the Transceiver Toolkit, I attempted to control the Transmitter Channel but I'm unable to get the board to transmit data. Pressing the Start button on that screen has no effect, and the Stop and Inject Error buttons remain permanently grayed out. I ran the link_test.tcl script included with the design and got this error: "Test stopped because checker cannot lock to incoming data pattern". Then I tried using data_pattern_generator_start and data_pattern_generator_is_generating commands to see if the generator is actually working, and I always got a negative result. Any suggestions?

First check that the transmitter and receiver are being enabled. There is a very specific reset sequence required on the Stratix IV devices, and I assume there is a similar requirement for the Stratix V devices. For example, check the PLLs are locked. Use SignalTap to probe the enables, status bits, lock bits etc. Use it to become familiar with the IP. You can then use SignalTap to probe the transmitter parallel output data (with respect to the parallel output data clock), and then another instance to probe the receiver parallel input data. At least then you can see whether you have sane data leaving the transmitter and nothing or something coming in the receiver. Cheers, Dave

Thanks for the tip, I used SignalTap to analyze the test example and found that the system is being held in reset. But I don't understand the purpose of the code that does so: wire system_reset_cnt; reg system_reset=1'b0; // Reset Counter to give active high reset to enable offset cancellation counter_128 cnt_128_isnt ( .clock (C100mhz), .q (system_reset_cnt) ); always @ (posedge C100mhz) begin if (system_reset_cnt >= 8'd128) begin system_reset <= 1'b1; end end What does the line 'Reset Counter to give active high reset to enable offset cancellation' mean?

--- Quote Start --- What does the line 'Reset Counter to give active high reset to enable offset cancellation' mean? --- Quote End --- The Stratix IV handbook, and I would guess the Stratix V handbook, discuss the initialization sequence for the transceiver blocks. Enabling the transceivers involves allowing for the input offset voltage calibration to complete, PLLs to lock, and the sequencing of analog and digital reset controls. Your only solution is to sit down and read the handbook. However, while you do this, you can cheat a little. Create a simple system with a few GPIOs and connect those GPIOs to the transceiver block controls (eg., an SOPC system with a JTAG-to-Avalon-MM bridge and a PIO). Then in software toggle each signal while using SignalTap to capture the status bits from the transceiver block. Use that to understand what happens in the hardware. Then in parallel, create a Modelsim testbench and implement similar control signal sequences. You will see that the Modelsim model produces a different result - usually a much faster time for a status bit to change state - but overall the same sequence will occur. Write your own reset controller to implement the appropriate sequence; use a counter to wait for the 'expected' status signal assertions, use generics to change the values for simulation via hardware, use timeout counts, so that you can generate your own status outputs (eg., PLL did not lock due to missing clock, or missing input cable). I'm kind-of surprised that Altera just doesn't supply an IP block to implement the correct reset sequencer. But, they don't, and their example code is not always that great, so shrug your shoulders, roll up your sleeves, and write it yourself. This is probably not what you wanted to hear, but it'll help you get things working. Cheers, Dave

Thanks for the help, Dave. I tried implementing the second Stratix V example (4-channel 6.443 Gbps links) and this one is transmitting, but the PLL isn't locking. Based on what I read in the "Transceiver Reset Control in Stratix V Devices" handbook, the transceiver block is being reset properly, and the tx_ready and reconfig_busy status pins are showing 1 and 0 respectively as expected. But pll_locked and rx_ready are both 0. The PLL clock appears to be working according to Signal Tap, and I'm able to measure its frequency by connecting a scope to the associated trigger, and it appears to be 644.53 MHz, as expected. I tries simulating the file in Modelsim, but I ran into this fatal error - http://www.altera.com/support/kdb/solutions/spr376737.html Sadly there doesn't seem to be any workarounds Any other ways I can figure out why the PLL isn't locking?

--- Quote Start --- I tried implementing the second Stratix V example (4-channel 6.443 Gbps links) and this one is transmitting, but the PLL isn't locking. --- Quote End --- Be a little more specific please. If its transmitting, then the TX PLL must be working. So its the receiver PLL that is not locking? --- Quote Start --- Based on what I read in the "Transceiver Reset Control in Stratix V Devices" handbook, the transceiver block is being reset properly, and the tx_ready and reconfig_busy status pins are showing 1 and 0 respectively as expected. But pll_locked and rx_ready are both 0. --- Quote End --- Study the document carefully. Some of the signals are for the transmitter block, other are for the receiver block. There are also reset controls that you might need to deassert. --- Quote Start --- I tries simulating the file in Modelsim, but I ran into this fatal error - http://www.altera.com/support/kdb/solutions/spr376737.html Sadly there doesn't seem to be any workarounds --- Quote End --- Try creating the component in Verilog rather than VHDL. Perhaps that works? Or use Modelsim-SE full edition if you have access to a license. --- Quote Start --- Any other ways I can figure out why the PLL isn't locking? --- Quote End --- Which PLL first? The receiver PLLs need to be connected to a reference clock and started in lock-to-reference mode. Then once data is present on the input and toggling, the receiver PLL can transition to lock-to-data mode. This transition can be configured to be automatic. Cheers, Dave

Transceiver Toolkit Design Example | Altera Community

14 Replies

Altera_Forum
Honored Contributor
14 years ago
Hi Dave,

Thanks for your advice.

I am interested in making a device that outputs multiple channels of test patterns over SMA (single-ended, into 50 Ohm loads) at 10 Gbps or faster. Since the dev board has 7x channels wired to SMA (7x transmit, 7x receive, all of them diff pairs), I think I should be able to make at least 6 channels output in sync. (The overall goal is to make a "poor man's 0 Gbps multichannel arbitrary pattern generator".)

What is your opinion on how likely I am to be able to get reasonable waveforms out of the SMAs if I terminate one of the differential outputs, and transmit only single-ended signals?

As best I can tell, the Stratix IV transceiver dev board that provides 10+Gbps transceivers is very expensive (~$13k), versus ~$5k for the Stratix V dev board, which is why I'm currently considering the Stratix V-based board.

I'm willing to wait a few months for the dev boards to start using non-engineering-sample chips. I heard a rumour that this will happen sometime in March/April, but I'd be grateful for more information on the timing here, if anyone has any.

Cheers,
Peter
Altera_Forum
Honored Contributor
14 years ago
Hi Peter,

--- Quote Start ---

I am interested in making a device that outputs multiple channels of test patterns over SMA (single-ended, into 50 Ohm loads) at 10 Gbps or faster.

--- Quote End ---
The code for generating arbitrary PRBS/LFSRs in parallel-mode in the fabric for being serialized in the transmitters is here:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial.pdf)
http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial_src.zip)

I need to finish writing the transmitter section in the tutorial, however, the code is there.

--- Quote Start ---

Since the dev board has 7x channels wired to SMA (7x transmit, 7x receive, all of them diff pairs), I think I should be able to make at least 6 channels output in sync. (The overall goal is to make a "poor man's 0 Gbps multichannel arbitrary pattern generator".)

--- Quote End ---
The Stratix V GX Development Kit might be a better option. Samtec have HSMC-to-SMA and PCIe-to-SMA breakout cables. Those cables let you access many more transceiver channels.

--- Quote Start ---

What is your opinion on how likely I am to be able to get reasonable waveforms out of the SMAs if I terminate one of the differential outputs, and transmit only single-ended signals?

--- Quote End ---
I've done it before for LVDS, look at page 60:

http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf)

Its not just a matter of simply terminating the signal with a resistor. You have to terminate it into the right kind of network. In the case of the network on p60, to the LVDS driver, it looks like a 100-Ohm load. To the RF input, it looks like a 50-ohm source. You can do the same for the transmitters.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Hi Dave,

Thanks very much.

The board I was thinking about getting was the Stratix V transceiver dev kit ( altera.com/products/devkits/altera/kit-transceiver-si-stratix-v.html ). Is this what you were suggesting too? On the dev kit list page ( altera.com/products/devkits/kit-dev_platforms.jsp ) I don't see any other suitable Stratix V dev kits -- is there something else available that I should look into?

Thanks for the advice on differential->single-ended conversion. Suppose I'm given the p and n SMA outputs on a dev board, what do you think is the easiest way to appropriately terminate the n output? e.g. does there exist some pre-made conversion board that I can buy, or will I need to make my own little PCB with the appropriate matching network?

Thanks,
Peter
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

The board I was thinking about getting was the Stratix V transceiver dev kit ( altera.com/products/devkits/altera/kit-transceiver-si-stratix-v.html ). Is this what you were suggesting too?

--- Quote End ---
There are three Stratix V kits, two have web pages, and the one I was recommending does not. Go to the Stratix V handbook page, and look down the bottom under development kits:

http://www.altera.com/literature/lit-stratix-v.jsp

You'll see links there. There is the SI kit, the 100G kit, and the Stratix V GX Development kit (the one I was recommending). I have the Stratix IV GX Development kit. There are also kits for the Stratix IV GT FPGAs.

--- Quote Start ---

Thanks for the advice on differential->single-ended conversion. Suppose I'm given the p and n SMA outputs on a dev board, what do you think is the easiest way to appropriately terminate the n output? e.g. does there exist some pre-made conversion board that I can buy, or will I need to make my own little PCB with the appropriate matching network?

--- Quote End ---
I haven't seen anything pre-made. You'll have to make something up.

Cheers,
Dave

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Transceiver Toolkit Design Example

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