Forum Discussion
Altera_Forum
Honored Contributor
13 years agoYes the P in PLL stands for 'phase' but when a PLL locks to the phase of the input, this means it is also frequency locked (see the second paragraph of the Wikipedia PLL article, unfortunately I can't post the link).
Since the Rx-PLL will be frequency locked to the incoming data stream I still don't understand how any slippage/drifting can occur and why the rate-matching FIFO is needed.