Transceiver Pin Assignment Problem in Pin Planner for Stratix IV GX 230 FPGA

Hi,

I am doing IO assignment analysis and Pin Planning check for one of our FPGA design. Design is having multiple high speed Tx/Rx serial link and other I/O standard requirement. To name a few like PCIe, Seraillite-II etc... Legality of Pin assignment in our FPGA design is passing except for all the transceiver pin assignments. Whenever, I am assigning the pin as per our already planned pin allocation ( i.e. Tx & Rx pin of QL0, QL1, QR0 etc..), I/O Check by Pin Planner is giving following error message for each of the transceiver pin assignment. For example :

error: differential i/o output pin rix_peg_txd[5](n) is assigned to a gxb transmitter location ab37. however, it must be assigned to a differential output location

When I delete all the pin assignment for Transceiver related signal in Pin Planner, then Live I /O Check passes in the Pin Planner. If I also only assign like IOBANK_QL0 or IOBANK_QRO etc.. under Location in Pin Planner, I/O Check passes.

With above changes to make I/O Check passing, our Fitter run thereafter fails and throws following error messages :

error: i/o standard "1.4-v pcml" is not valid for i/o pad "rix_peg_txd[1](n)". only pins connected to gxb transceiver blocks can use this standard.

Just for info, I/O Standard used as 1.4 V PCML for all our Transceiver pin of selected device EP4SGX230KF40C2ES.

I am not able to figure out the reason for this. Any suggestion, Please. Early response is highly appreciated.