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Altera_Forum
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16 years ago

Transceiver Pin Assignment Problem in Pin Planner for Stratix IV GX 230 FPGA

Hi, I am doing IO assignment analysis and Pin Planning check for one of our FPGA design. Design is having multiple high speed Tx/Rx serial link and other I/O standard requirement. To name a few ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Basically you can't have transceiver pins in your design and not connect them to transceiver blocks. It's okay to make the pin assignment but if you're not going to connect the pin in the design, you need to remove it from the top level design.

Jake