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If you are receiving and transmitting SDI video, then your transceiver configuration will not involve inserting/removing idles. If you are transferring a video stream from one source to another, then you can use FIFOs (in the FPGA fabric) for storing frames, and that will simply delay the video stream.
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I'm afraid that will not work. The problem with SDI video is exactly that you cannot insert/remove idles (just in case it wasn't clear, the signal comes from another device so it does not share a common clock source with the FPGA). If I understand correctly, what you're telling me to try is this:
SDI_in --> XCVR_0 --> ( FIFO ) --> XCVR_1 --> SDI_out
The parenthesis indicate that the FIFO is in the FPGA fabric, the rate-match FIFOs are included in the XCVR.
Let me throw some numbers (not accurate nor real, just for demonstration purposes). Lets say both XCVRs are clocked with the same reference of 100M. Now, if the incoming video signal is running slightly off at 99M then the CDR in XCVR_0 will recover a 99M clock. You feed that into the FPGA's fabric FIFO and then extract it with the output transceiver's clock of 100M.
At this point you have a 99M source pushing data into the FIFO and a 100M sink pulling data out, since the sink is running faster it will have to make up samples, 1M of them in a second in this simple example. The same happens the other way around if the video signal is running at 101M, you will have an excess of 1M samples in a second which need to be discarded.
Am I understanding incorrectly the way you say the transceivers work? Can a Tx transceiver clocked at 100M actually output data at 99M/101M without inserting or removing idles? The only way I've been able to do this is by connecting the recovered clock from XCVR_0 to a fPLL and then feed that as a reference for XCVR_1, this is not a solution though since you can only really use one fPLL per bank so there would be a bunch of Tx XCVRs you wouldn't be able to use.
Once again, thank you for your help!! =)
Regards,
Sebastian.
Honored Contributor
