--- Quote Start ---
I'm using the transceivers to receive and transmit SDI video, this means there's no room for idle character insertion which is, if I understand correctly, what the rate-match FIFO does, right?
--- Quote End ---
The FIFOs are there primarily for clock domain crossing. You could design a system with a common clock source, yet many many transceivers, and although they are phase-locked to the same source, the relative clock phases used by the transmitters, receivers (clock-and-data recovery unit PLL), and the FPGA clock domain, will all be different. The FIFOs allow you to bring data in from one receiver, cross into the FPGA fabric, and then cross over to a transmitter.
If you are receiving and transmitting SDI video, then your transceiver configuration will not involve inserting/removing idles. If you are transferring a video stream from one source to another, then you can use FIFOs (in the FPGA fabric) for storing frames, and that will simply delay the video stream.
Create a simulation containing two transceiver interfaces (TX+RX in two different blocks), connect the Avalon-ST video streams, and assuming that setup works fine, you should be able to see how to scale things so that the FPGA is a video multiplexing switch.
Cheers,
Dave
Honored Contributor
