Hi- I use 10 Tranceiver PHY. ←(Tx only, Simplex)Tranceiver PHY 10 is OK.But there is an error when adding one more. I use following IP component 10 Tanceiver PHY, + 10 Tanceiver Reset, + 8 fpll +2 CMU pll and add 1 Tanceiver PHY + 1 Tanceiver Reset + 1 Tanceiver CMU pll How do you fix it? Error message is below.. -> Error(14996): The Fitter failed to find a legal placement for all periphery components -> Info(14987): The following components had the most difficulty being legally placed: -> Info(175029): auto-promoted clock driver u7_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (14%) -> Info(175029): HSSI_DUPLEX_CHANNEL_CLUSTER ePI_tx3[1]~CLUSTER~HSSI_TX_CHANNEL_CLUSTER5~HSSI_DUPLEX_CHANNEL_CLUSTER5 (14%) -> Info(175029): auto-promoted clock driver u8_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (14%) -> Info(175029): auto-promoted clock driver u1_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (13%) -> Info(175029): auto-promoted clock driver u7_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (7%) -> Info(175029): auto-promoted clock driver u8_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (7%) -> Info(175029): auto-promoted clock driver u1_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (7%) -> Info(175029): HSSI_DUPLEX_CHANNEL_CLUSTER ePI_tx8[0]~CLUSTER~HSSI_TX_CHANNEL_CLUSTER14~HSSI_DUPLEX_CHANNEL_CLUSTER14 (6%) -> Info(175029): HSSI_DUPLEX_CHANNEL_CLUSTER ePI_tx2[0]~CLUSTER~HSSI_TX_CHANNEL_CLUSTER1~HSSI_DUPLEX_CHANNEL_CLUSTER2 (5%) -> Info(175029): auto-promoted clock driver u5_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (4%) -> Error(14986): After placing as many components as possible, the following errors remain: -> Error(175001): The Fitter cannot place 1 HSSI_PIPE_GEN3, -> which is within Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP -> A10_XCVR_native_altera_xcvr_native_a10_180_ghkxcjq. -> Info(14596): Information about the failing component(s): -> Info(175028): The HSSI_PIPE_GEN3 name(s): u5_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_pipe_gen3.inst_twentynm_hssi_pipe_gen3 -> Error(16234): No legal location could be found out of 24 considered location(s). Reasons why each location could not be used are summarized below: -> Error(175006): There is no routing connectivity between the HSSI_PIPE_GEN3 and destination HSSI_TX_PCS_PMA_INTERFACE -> Info(175027): Destination: HSSI_TX_PCS_PMA_INTERFACE u5_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pcs_pma_interface.inst_twentynm_hssi_tx_pcs_pma_interface -> Info(175013): The HSSI_TX_PCS_PMA_INTERFACE is constrained to the region (0, 7) to (0, 109) due to related logic -> Error(175022): The HSSI_PIPE_GEN3 could not be placed in any location to satisfy its connectivity requirements -> Info(175021): The HSSI_TX_PCS_PMA_INTERFACE was placed in location HSSITXPCSPMAINTERFACE_1C1 -> Info(175029): 4 locations affected -> Info(175029): HSSIPIPEGEN3_1C3 -> Info(175029): HSSIPIPEGEN3_1C4 -> Info(175029): HSSIPIPEGEN3_1D1 -> Info(175029): HSSIPIPEGEN3_1E4 -> Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP A10_XCVR_native_altera_xcvr_native_a10_180_ghkxcjq. -> Info(14596): Information about the failing component(s): -> Info(175028): The HSSI_DUPLEX_CHANNEL_CLUSTER name(s): ePI_tx5[1]~CLUSTER~HSSI_TX_CHANNEL_CLUSTER9~HSSI_DUPLEX_CHANNEL_CLUSTER9 -> Error(16234): No legal location could be found out of 24 considered location(s). Reasons why each location could not be used are summarized below: -> Error(175006): There is no routing connectivity between the HSSI_DUPLEX_CHANNEL_CLUSTER and destination HSSI_PIPE_GEN3 -> Info(175027): Destination: HSSI_PIPE_GEN3 u4_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_pipe_gen3.inst_twentynm_hssi_pipe_gen3 -> Info(175013): The HSSI_PIPE_GEN3 is constrained to the region (0, 9) to (0, 111) due to related logic -> Error(175022): The HSSI_DUPLEX_CHANNEL_CLUSTER could not be placed in any location to satisfy its connectivity requirements -> Info(175021): The HSSI_PIPE_GEN3 was placed in location HSSIPIPEGEN3_1C1 -> Info(175029): 1 location affected -> Info(175029): HSSI_DUPLEX_CHANNEL_CLUSTER containing PIN_AH32

hi SungThanks for the update.Glad to see that the issue was resolved.

Forum Discussion

sung_chul

New Contributor

3 years ago

Solved

Tranceiver PHY or pll fitting error!

Hi-

I use 10 Tranceiver PHY. ←(Tx only, Simplex)
Tranceiver PHY 10 is OK.
But there is an error when adding one more.

I use following IP component

10 Tanceiver PHY, +

10 Tanceiver Reset, +

8 fpll +2 CMU pll

and add 1 Tanceiver PHY + 1 Tanceiver Reset + 1 Tanceiver CMU pll

How do you fix it?

Error message is below..

-> Error(14996): The Fitter failed to find a legal placement for all periphery components
-> Info(14987): The following components had the most difficulty being legally placed:
-> Info(175029): auto-promoted clock driver u7_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (14%)
-> Info(175029): HSSI_DUPLEX_CHANNEL_CLUSTER ePI_tx3[1]~CLUSTER~HSSI_TX_CHANNEL_CLUSTER5~HSSI_DUPLEX_CHANNEL_CLUSTER5 (14%)
-> Info(175029): auto-promoted clock driver u8_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (14%)
-> Info(175029): auto-promoted clock driver u1_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (13%)
-> Info(175029): auto-promoted clock driver u7_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (7%)
-> Info(175029): auto-promoted clock driver u8_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (7%)
-> Info(175029): auto-promoted clock driver u1_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (7%)
-> Info(175029): HSSI_DUPLEX_CHANNEL_CLUSTER ePI_tx8[0]~CLUSTER~HSSI_TX_CHANNEL_CLUSTER14~HSSI_DUPLEX_CHANNEL_CLUSTER14 (6%)
-> Info(175029): HSSI_DUPLEX_CHANNEL_CLUSTER ePI_tx2[0]~CLUSTER~HSSI_TX_CHANNEL_CLUSTER1~HSSI_DUPLEX_CHANNEL_CLUSTER2 (5%)
-> Info(175029): auto-promoted clock driver u5_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_tx_clk_out~CLKENA0 (4%)
-> Error(14986): After placing as many components as possible, the following errors remain:
-> Error(175001): The Fitter cannot place 1 HSSI_PIPE_GEN3,
-> which is within Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP
-> A10_XCVR_native_altera_xcvr_native_a10_180_ghkxcjq.
-> Info(14596): Information about the failing component(s):
-> Info(175028): The HSSI_PIPE_GEN3 name(s): u5_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_pipe_gen3.inst_twentynm_hssi_pipe_gen3
-> Error(16234): No legal location could be found out of 24 considered location(s). Reasons why each location could not be used are summarized below:
-> Error(175006): There is no routing connectivity between the HSSI_PIPE_GEN3 and destination HSSI_TX_PCS_PMA_INTERFACE
-> Info(175027): Destination: HSSI_TX_PCS_PMA_INTERFACE u5_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pcs_pma_interface.inst_twentynm_hssi_tx_pcs_pma_interface
-> Info(175013): The HSSI_TX_PCS_PMA_INTERFACE is constrained to the region (0, 7) to (0, 109) due to related logic
-> Error(175022): The HSSI_PIPE_GEN3 could not be placed in any location to satisfy its connectivity requirements
-> Info(175021): The HSSI_TX_PCS_PMA_INTERFACE was placed in location HSSITXPCSPMAINTERFACE_1C1
-> Info(175029): 4 locations affected
-> Info(175029): HSSIPIPEGEN3_1C3
-> Info(175029): HSSIPIPEGEN3_1C4
-> Info(175029): HSSIPIPEGEN3_1D1
-> Info(175029): HSSIPIPEGEN3_1E4
-> Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP A10_XCVR_native_altera_xcvr_native_a10_180_ghkxcjq.
-> Info(14596): Information about the failing component(s):
-> Info(175028): The HSSI_DUPLEX_CHANNEL_CLUSTER name(s): ePI_tx5[1]~CLUSTER~HSSI_TX_CHANNEL_CLUSTER9~HSSI_DUPLEX_CHANNEL_CLUSTER9
-> Error(16234): No legal location could be found out of 24 considered location(s). Reasons why each location could not be used are summarized below:
-> Error(175006): There is no routing connectivity between the HSSI_DUPLEX_CHANNEL_CLUSTER and destination HSSI_PIPE_GEN3
-> Info(175027): Destination: HSSI_PIPE_GEN3 u4_A10_XCVR_native|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_pipe_gen3.inst_twentynm_hssi_pipe_gen3
-> Info(175013): The HSSI_PIPE_GEN3 is constrained to the region (0, 9) to (0, 111) due to related logic
-> Error(175022): The HSSI_DUPLEX_CHANNEL_CLUSTER could not be placed in any location to satisfy its connectivity requirements
-> Info(175021): The HSSI_PIPE_GEN3 was placed in location HSSIPIPEGEN3_1C1
-> Info(175029): 1 location affected
-> Info(175029): HSSI_DUPLEX_CHANNEL_CLUSTER containing PIN_AH32

skbeh
3 years ago
hi Sung
Thanks for the update.
Glad to see that the issue was resolved.

11 Replies

skbeh
Contributor
3 years ago
Hi Sir
To further troubleshoot the compilation/fitting error, can you please attach your Quartus project (.qar)?
- sung_chul
  New Contributor
  3 years ago
  Hi skbeh
  
  This is Quartus 18.0 Pro
  
  ePI_Top.v
  
  // XCVR Interface 11
  
  Add 470~510 Line
  
  and
  
  //epi_data #10
  
  Add 661~669 Line
  
  So, Error Occur
  
  ps.gxb_ref_clk1 ~ 11 is open
  ePI_TX_18_0_0_219.qar36.1 MB
skbeh
Contributor
3 years ago
Hi Sir
Within the same transceiver bank, only transceiver channel 1 or channel 4 can be used as CMU PLL, channels 0, 2, 3, and 5 cannot be configured as a CMU PLL.
So make sure either channel 1 or channel 4 is being used as CMU PLL.

When you added 1 Tranceiver PHY + 1 Tranceiver Reset + 1 Tranceiver CMU pll, make sure the '1 Tranceiver PHY' and '1 Tranceiver CMU pll' are within the same transceiver bank.

Alternatively, you can try add ATX PLL instead of CMU PLL, and enable the xN non-bonded clock output port in the ATX PLL GUI (under Master Clock Generation Block tab) if you use the ATX PLL to drive transceivers beyond a single 6-pack.
- sung_chul
  New Contributor
  3 years ago
  Hi- skbeh
  
  I tried two ways.
  
  But, I didn't get any
  
  No Success!
  
  8 fpll + 3 atx pll
  ePI_TX_18_0_0_219.qar36.6 MB
skbeh
Contributor
3 years ago
Hi Sir

I can't compile the design further due to errors below, looks like absolute path are being used in your design.

Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File D:/EPI_TX/DISPLAY_99232_341_682_WITH_ADC_EPI_211116/src/vector_rom/vector_htol.hex for ROM instance u0_epi_data|u_vector_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File D:/EPI_TX/DISPLAY_99232_341_682_WITH_ADC_EPI_211116/src/lock_rom/lock_rom.hex for ROM instance u0_epi_data|u_lock_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/vector_rom1/IPS_AEQ_CT_ILT_1Line.mif for ROM instance u1_epi_data|u1_vector_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/lock_rom1/TTL.mif for ROM instance u1_epi_data|u1_lock_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/vector_rom2/Make_1th_2th-data.mif for ROM instance u2_epi_data|u2_vector_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/lock_rom2/TTL_193674.mif for ROM instance u2_epi_data|u2_lock_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/vector_rom3/Make_1th_2th-data.mif for ROM instance u3_epi_data|u3_vector_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/lock_rom3/TTL_193674.mif for ROM instance u3_epi_data|u3_lock_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/vector_rom4/Make_1th_2th-data.mif for ROM instance u4_epi_data|u4_vector_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/lock_rom4/TTL_193674.mif for ROM instance u4_epi_data|u4_lock_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/vector_rom5/Make_1th_2th-data.mif for ROM instance u5_epi_data|u5_vector_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/lock_rom5/TTL_193674.mif for ROM instance u5_epi_data|u5_lock_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/vector_rom6/Make_1th_2th-data.mif for ROM instance u6_epi_data|u6_vector_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/lock_rom6/TTL_193674.mif for ROM instance u6_epi_data|u6_lock_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/vector_rom7/Make_1th_2th-data.mif for ROM instance u7_epi_data|u7_vector_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/lock_rom7/TTL_193674.mif for ROM instance u7_epi_data|u7_lock_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/vector_rom8/Make_1th_2th-data.mif for ROM instance u8_epi_data|u8_vector_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/lock_rom8/TTL_193674.mif for ROM instance u8_epi_data|u8_lock_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/vector_rom9/Make_1th_2th-data.mif for ROM instance u9_epi_data|u9_vector_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/lock_rom9/TTL_193674.mif for ROM instance u9_epi_data|u9_lock_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/vector_rom10/Make_1th_2th-data.mif for ROM instance u10_epi_data|u10_vector_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
Error(127001): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File E:/EPI_TX/DISPLAY_1/src/lock_rom10/TTL_193674.mif for ROM instance u10_epi_data|u10_lock_rom|rom_1port_0|altera_syncram_component|auto_generated|altsyncram1|ALTSYNCRAM
- sung_chul
  New Contributor
  3 years ago
  Hi skbeh
  
  Yes, of course!
  
  I have written
  
  -------------------------
  
  No Success!
  
  8 fpll + 3 atx pll
  
  -------------------------
  
  Like you said, I used "atx pll", so result Fail
  
  and ..
  
  Where to connect mcgb_serial_clk?
skbeh
Contributor
3 years ago
Hi Sir
I can't duplicate the fitter error as you describe earlier due to your design used absolute path to some .mif file, the compilation fail at the very beginning and not yet reach the fitter error stage. Can you edit/change your design about the absolute path and re-attach?

In between,
1) In Pin Planner, I noticed only gxb_ref_clk0/1/2/3 being assigned to a pin, but in ePI_Top.v got additional gxb_ref_clk4-10 not being assigned. Pls try
a) share the gxb_ref_clk0 to all transceiver channels in the same Bank 1C
b) share the gxb_ref_clk1 to all transceiver channels in the same Bank 1D
c) share the gxb_ref_clk2 to all transceiver channels in the same Bank 1E
d) share the gxb_ref_clk3 to all transceiver channels in the same Bank 1F

2) In the Transceiver Native PHY IP GUI, try change the 'channel bonding mode' to 'Not bonded'
- sung_chul
  New Contributor
  3 years ago
  Hi skbeh
  
  1) gxb_ref_clk0~11 all pin is opened
  Only the pin assignment in the "ePI_Top.v" did that.
  
  It is open outside the FPGA
  
  2) How to add a file with an absolute path?
  
  including mif file directory is below
  
  drives\D\EPI_TX\DISPLAY_99232_341_682_WITH_ADC_EPI_211116\src\lock_rom\lock_rom.hex
  drives\E\EPI_TX\DISPLAY_1\src\lock_rom1\TTL.mif
  
  drives\E\EPI_TX\DISPLAY_1\src\lock_rom2\TTL_193674.mif
  
  drives\E\EPI_TX\DISPLAY_1\src\lock_rom3\TTL_193674.mif
  
  drives\E\EPI_TX\DISPLAY_1\src\lock_rom4\TTL_193674.mif
  
  drives\E\EPI_TX\DISPLAY_1\src\lock_rom5\TTL_193674.mif
  
  :
  
  :
  
  --------------------------------------------------------------------------------
  
  drives\D\EPI_TX\DISPLAY_99232_341_682_WITH_ADC_EPI_211116\src\vector_rom\vector_rom.hex
  
  drives\E\EPI_TX\DISPLAY_1\src\vector_rom1\IPS_AEQ_CT_ILT_1Line.mif
  
  drives\E\EPI_TX\DISPLAY_1\src\vector_rom2\Make_1th_2th-data.mif
  
  drives\E\EPI_TX\DISPLAY_1\src\vector_rom3\Make_1th_2th-data.mif
  
  drives\E\EPI_TX\DISPLAY_1\src\vector_rom4\Make_1th_2th-data.mif
  
  :
  
  :
  
  Thanks!
  ePI_TX_18_0_0_219.qar36.1 MB
skbeh
Contributor
3 years ago
To pass the compilation of this project:
1) In the Transceiver Native PHY IP GUI, change the 'Tx channel bonding mode' to 'Not bonded'
2) Comment out tx_bonding_clocks_phy1 until tx_bonding_clocks_phy11 at ePI_Top.v
//.tx_bonding_clocks (tx_bonding_clocks_phy1),
...
...
//.tx_bonding_clocks (tx_bonding_clocks_phy11),

3) gxb_ref_clk4-7 is undefined in ePI_Top.v, add below line.
input wire gxb_ref_clk4,gxb_ref_clk5,gxb_ref_clk6,gxb_ref_clk7,

Attached is the simplify version of this project.
ePI_TX_21_4_0_67_Passed.qar10.9 MB
- sung_chul
  New Contributor
  3 years ago
  Hi- skbeh
  
  Thank you for your interest.
  I solved this problem.
  I got a hint from the sample files on the page of Angelica_S_Intel
  
  "Arria10 Transceiver PHY Basic Design Examples"
  All 24 ports are working fine.
  Thank you again for your interest.
  
  Thanks!
  
  Preview
skbeh
Contributor
3 years ago
hi Sung
Thanks for the update.
Glad to see that the issue was resolved.

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