Forum Discussion
New ContributorTranceiver PHY or pll fitting error!
hi Sung
Thanks for the update.
Glad to see that the issue was resolved.
ContributorHi Sir
Within the same transceiver bank, only transceiver channel 1 or channel 4 can be used as CMU PLL, channels 0, 2, 3, and 5 cannot be configured as a CMU PLL.
So make sure either channel 1 or channel 4 is being used as CMU PLL.
When you added 1 Tranceiver PHY + 1 Tranceiver Reset + 1 Tranceiver CMU pll, make sure the '1 Tranceiver PHY' and '1 Tranceiver CMU pll' are within the same transceiver bank.
Alternatively, you can try add ATX PLL instead of CMU PLL, and enable the xN non-bonded clock output port in the ATX PLL GUI (under Master Clock Generation Block tab) if you use the ATX PLL to drive transceivers beyond a single 6-pack.
New ContributorHi- skbeh
I tried two ways.
But, I didn't get any
No Success!
8 fpll + 3 atx pll
