Forum Discussion
Tranceiver PHY or pll fitting error!
- 3 years ago
hi Sung
Thanks for the update.
Glad to see that the issue was resolved.
Hi Sir
I can't duplicate the fitter error as you describe earlier due to your design used absolute path to some .mif file, the compilation fail at the very beginning and not yet reach the fitter error stage. Can you edit/change your design about the absolute path and re-attach?
In between,
1) In Pin Planner, I noticed only gxb_ref_clk0/1/2/3 being assigned to a pin, but in ePI_Top.v got additional gxb_ref_clk4-10 not being assigned. Pls try
a) share the gxb_ref_clk0 to all transceiver channels in the same Bank 1C
b) share the gxb_ref_clk1 to all transceiver channels in the same Bank 1D
c) share the gxb_ref_clk2 to all transceiver channels in the same Bank 1E
d) share the gxb_ref_clk3 to all transceiver channels in the same Bank 1F
2) In the Transceiver Native PHY IP GUI, try change the 'channel bonding mode' to 'Not bonded'
Hi skbeh
1) gxb_ref_clk0~11 all pin is opened
Only the pin assignment in the "ePI_Top.v" did that.
It is open outside the FPGA
2) How to add a file with an absolute path?
including mif file directory is below
drives\D\EPI_TX\DISPLAY_99232_341_682_WITH_ADC_EPI_211116\src\lock_rom\lock_rom.hex
drives\E\EPI_TX\DISPLAY_1\src\lock_rom1\TTL.mif
drives\E\EPI_TX\DISPLAY_1\src\lock_rom2\TTL_193674.mif
drives\E\EPI_TX\DISPLAY_1\src\lock_rom3\TTL_193674.mif
drives\E\EPI_TX\DISPLAY_1\src\lock_rom4\TTL_193674.mif
drives\E\EPI_TX\DISPLAY_1\src\lock_rom5\TTL_193674.mif
:
:
--------------------------------------------------------------------------------
drives\D\EPI_TX\DISPLAY_99232_341_682_WITH_ADC_EPI_211116\src\vector_rom\vector_rom.hex
drives\E\EPI_TX\DISPLAY_1\src\vector_rom1\IPS_AEQ_CT_ILT_1Line.mif
drives\E\EPI_TX\DISPLAY_1\src\vector_rom2\Make_1th_2th-data.mif
drives\E\EPI_TX\DISPLAY_1\src\vector_rom3\Make_1th_2th-data.mif
drives\E\EPI_TX\DISPLAY_1\src\vector_rom4\Make_1th_2th-data.mif
:
:
Thanks!