Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

To handle interrupt from FPGA PB

Using Quaruts 14.0 on Linux 64bit on Altera's SOC dev kit.

There 2 example from Altera that i am using.

The Altera-SoCFPGA-HardwareLib-GPIO-CV-GNU and Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU.

The FPGA side is GHRD from Altera.

I am trying to catch interrupt while pushing FPGA push button. Nothing happened on HPS side.

What is missing on the flow?

The actual code is:

alt_int_global_init();

alt_int_cpu_init();

alt_int_cpu_enable();

alt_int_global_enable();

target = 0x3;

alt_int_dist_target_set(ALT_INT_INTERRUPT_F2S_FPGA_IRQ0, target);

alt_int_dist_trigger_set(ALT_INT_INTERRUPT_F2S_FPGA_IRQ0, ALT_INT_TRIGGER_LEVEL);

alt_int_dist_enable(ALT_INT_INTERRUPT_F2S_FPGA_IRQ0);

alt_int_isr_register(ALT_INT_INTERRUPT_F2S_FPGA_IRQ0, fpga_isr_callback, NULL);

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    See you all program execution in debugger ? No errors ?

    GHRD from Altera may exactly not connect FPGA PBs to interrupt inputs.

    My FPGA programmer make special design and invert PB values, because interrupts take in on logical 1, and pressing of PB generate 0, 1 in free state.

    And we don't know, on what input of GIC (generic interrupt controller) is come in our signal -- may be 64 from 72 to 135 (ALT_INT_INTERRUPT_F2S_FPGA_IRQ*) and 207 -- ALT_INT_INTERRUPT_FPGA_MAN_IRQ.

    I write polling all 0..255 function and see only 71 == ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ often :)

    P.S. Now I handle interrupt from both FPGAs PBs, include .zip with .sof for ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 ?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I found solution.

    The FPGA PBs actually masked interrupt, so there is need to unmask.

    According to GHRD it comes from ALT_INT_INTERRUPT_F2S_FPGA_IRQ1 which is true.

    Thanks for help.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Yes, THANKS ! ! ! :)

    In which Altera document described this interrupt pin ?

    We edit GHRD for get interrupt out from PBs.

    Gxk, you plainly in DS-5 ?

    Irritates lossing of all debug breakpoints on new debug session (full red circles turn into empty red circles). May be medicine there ?

    And is methods to set cursor/caret/focus to source edit/view window by debugging in DS-5 ? Often escape to "Debug Control" :)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    My FPGA guy found description about PIO in ug_embedded_ip.pdf page 10-6

    I am using DS-5 and makefile and it is irritates me too, lossing all session breakpoints.

    It may be fixed in next version of DS-5 (optimistic). You may try to upgrade DS-5 from ARM.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I download last version of ug_embedded_ip.pdf from Altera for 11.0 Quartus, for 12-13-14 no changes ?

    In "Chapter 10. PIO Core" not described, what in SoC EDS GHRD its interrupt output is connected to pin 1 of interrupt bus -- its common document ! :)

    Neverthless, where you know about this 1 pin ?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I understood, it comes from NIOS2 somehow.

    I can send it to you. What is the email?