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Altera_Forum
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11 years agoI download last version of ug_embedded_ip.pdf from Altera for 11.0 Quartus, for 12-13-14 no changes ?
In "Chapter 10. PIO Core" not described, what in SoC EDS GHRD its interrupt output is connected to pin 1 of interrupt bus -- its common document ! :) Neverthless, where you know about this 1 pin ?