Timing violations while integrating 2 display port example designs..

There is a possibility that the timing violation you are seeing could be a false path.

You need to review and check whether the timing path mentioned in the violation is relevant to the circuit's operation.

If you believe it is a false path, you can use the 'set_false_path' command to exclude that specific path from the timing analysis.

By the way, I noticed that you have posted two similar cases, one here (link: https://community.intel.com/t5/Intel-Quartus-Prime-Software/Timing-violation-while-integrating-2-display-port-example/m-p/1501202#M79114) and another one here.

Please note that it is not recommended to file duplicate cases, and we do not provide support for duplicated cases.

I will transition this thread to community support, while your other case will be handled by one of my colleagues.

If you have any further questions or concerns, please don't hesitate to reach out.

Thank you, and have a great day!

Best Regards,

Richard Tan

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