Forum Discussion
Honored ContributorTiming requirements to a part of a circuit
Does anybody know how to set timing requirements to a part of a circuit? I mean there is a critical part of a circuit that needs frequency optimization, and it's not rational to apply frequency constraint to all block. Thanks in advance.
23 Replies
Altera_ForumI meant that in my project mult has internal registers, which are clocked by fast_clk. OK, thank you, kaz.
- Altera_Forum--- Quote Start --- kaz, I'm using old version of cookbook (https://vk.com/doc-93602802_401608943?hash=1d128a921cdd322f95&dl=bd60b7ecbf49a6ca84), so there is some difference in projects, in old version they use pipelined multiplier, clocked by fast_clk. So when I click summary setup I can get some information about multiplier's set of registers. Of course if we use mult without pipelining we won't get any setup information. Which command is intended for enable only? OK, I'll look for it in Altera's documents... What I expect is to get some information about enabled registers: are requirements met or not, slacks, etc... If it's possible, of course. --- Quote End --- The two documents of cookbook have identical diagrams for enable multicycle example. The only difference is the figure number 1-16 & 1-18 sdc command for enable multicycle is given directly at bottom of page and has two parts multicycle and fanout. If project timing passes then it means all paths are ok including those on enable. To specifically find out about any given path then just follow the usual approach either in TQ GUI or by direct commands. I am not clear what do you mean by "without pipeline". There are registers on either side of mults, so these are valid timing paths.
- Altera_Forum
kaz, I'm using old version of cookbook (https://vk.com/doc-93602802_401608943?hash=1d128a921cdd322f95&dl=bd60b7ecbf49a6ca84), so there is some difference in projects, in old version they use pipelined multiplier, clocked by fast_clk. So when I click summary setup I can get some information about multiplier's set of registers. Of course if we use mult without pipelining we won't get any setup information. Which command is intended for enable only? OK, I'll look for it in Altera's documents...
What I expect is to get some information about enabled registers: are requirements met or not, slacks, etc... If it's possible, of course. - Altera_Forum
sorry I can't run projects now but a diagram and sdc will do.
Anyway I looked at the TA cookbook/figure 1-16 clock enable multicycle on page 1-25 and all registers are enabled(those into mult and those at mult outputs). In such cases you can apply sdc command for enable only and you don't need to worry about each single register. Are you looking at same design? - Altera_Forum
Here you are
- Altera_Forum
can you copy that Altera sdc example and design here or provide a link so I can better understand your viewpoint
- Altera_Forum
But I don't see these triggers with relaxed constraints into the report. Now I'm working with Clock Enable Multicycle Constraints project from TimeQuest TA cookbook and the only regs I see are regs from pipelined mult (they are not enabled). I can find them into name finder but I don't know how to add them to the report...
- Altera_Forum--- Quote Start --- In Altera's examples they set multicycle_path for enabled triggers and thus don't set timing requirements for them at all. However, sometimes this part of a project still needs timing requirements (maybe less strict). Is it possible set timing requirements for such piece of a project? Another problem that I've faced is difficulties in specifying triggers to set multicycling option to if they are "buried" into the project's hierarchy. --- Quote End --- In those examples the multicycle constraint is a timing constraint on all registers enabled by the enable signal. Without them setup relationship defaults to one clock period and hold to zero, with them you relax it e.g. to 2 for setup, 1 for hold or 3 for setup, 2 for hold. A convenient way to locate the nodes is to run TQ and then go to node finder and copy its path and name.
- Altera_Forum
In Altera's examples they set multicycle_path for enabled triggers and thus don't set timing requirements for them at all. However, sometimes this part of a project still needs timing requirements (maybe less strict). Is it possible set timing requirements for such piece of a project?
Another problem that I've faced is difficulties in specifying triggers to set multicycling option to if they are "buried" into the project's hierarchy. - Altera_Forum
Thank you for your answer
